- 11 9月, 2013 27 次提交
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由 Alexander Graf 提交于
This patch adds support for AArch64 in all the small corners of linux-user (primarily in image loading and startup code). Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NJohn Rigby <john.rigby@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-22-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-11-git-send-email-john.rigby@linaro.org [PMM: * removed some unnecessary #defines from syscall.h * catch attempts to use a 32 bit only cpu with aarch64-linux-user * termios stuff moved into its own patch * we specify our minimum uname version here now ] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
For newer target architectures, glibc can be picky about the kernel version: for example, it will not run on an aarch64 system unless the kernel reports itself as at least 3.8.0. Accommodate this by enhancing the existing support for faking the kernel version so that each target can optionally specify a minimum version: if the user doesn't force a specific fake version then we will override with the minimum required version only if the real host kernel version is insufficient. Use this facility to let aarch64 report a minimum of 3.8.0. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-21-git-send-email-peter.maydell@linaro.org
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由 Alexander Graf 提交于
Add the AArch64 termbits.h with all the target's termios related constants and structures. Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NJohn Rigby <john.rigby@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-20-git-send-email-peter.maydell@linaro.org [PMM: split out from another patch] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alexander Graf 提交于
Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NJohn Rigby <john.rigby@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-19-git-send-email-peter.maydell@linaro.org [PMM: pulled out from another patch; don't use is_a64() here; moved to linux-user from target-arm] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
On ARM, linux-user emulation includes NWFPE support for emulating the ancient FPA floating point coprocessor. This has long since been superseded by VFP and is only required for legacy binaries. The AArch64 linux-user target doesn't compile in NWFPE support, so make sure the relevant code is protected by suitable ifdefs. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-18-git-send-email-peter.maydell@linaro.org
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由 Andreas Schwab 提交于
This patch adds signal handling for AArch64. The code is based on the respective source in the Linux kernel. Signed-off-by: NAndreas Schwab <schwab@suse.de> Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NJohn Rigby <john.rigby@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-17-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-10-git-send-email-john.rigby@linaro.org [PMM: fixed style nits: tabs, long lines; pulled target_signal.h in from a later patch; it fits better here] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alexander Graf 提交于
Some syscall handlers have special code for ARM enabled that we don't need on AArch64. Exclude AArch64 in those cases. In other places we can share struct definitions with other targets or have to provide our own. With this patch applied, most syscall definitions in linux-user should be sound for AArch64. Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NJohn Rigby <john.rigby@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-16-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-9-git-send-email-john.rigby@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alexander Graf 提交于
The AArch64 syscall definitions are all publicly available in the Linux kernel. Let's add them to our linux-user emulation target, so that we can easily handle AArch64 syscalls. Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NJohn Rigby <john.rigby@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-15-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-8-git-send-email-john.rigby@linaro.org [PMM: changes relating to cpu_loop() removed as they are superseded by an earlier patch] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Add the main linux-user cpu loop for AArch64. Since AArch64 has a different system call interface, doesn't need to worry about FPA emulation and may in the future keep the prefetch/data abort information in different system registers, it's simplest just to use a completely separate loop from the 32 bit ARM target, rather than peppering it with ifdefs. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-14-git-send-email-peter.maydell@linaro.org
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由 Alexander Graf 提交于
32-bit ARM has a lot of different names for different types of CPUs it supports. On AArch64, we don't have this, so we really don't want to execute the 32-bit logic. Stub it out for AArch64 linux-user guests. Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NJohn Rigby <john.rigby@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-13-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-7-git-send-email-john.rigby@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alexander Graf 提交于
We want to be able to debug AArch64 guests. So let's add the respective gdb stub functions and xml descriptions that allow us to do so. Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NJohn Rigby <john.rigby@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-12-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-6-git-send-email-john.rigby@linaro.org [PMM: dropped unused fp regs XML for now; moved 64 bit only functions to new gdbstub64.c; these are hooked up in AArch64CPU, not via ifdefs in ARMCPU] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alexander Graf 提交于
We should translate AArch64 mode separately from AArch32 mode. In AArch64 mode, registers look vastly different, instruction encoding is completely different, basically the system turns into a different machine. So let's do a simple if() in translate.c to decide whether we can handle the current code in the legacy AArch32 code or in the new AArch64 code. So far, the translation always complains about unallocated instructions. There is no emulator functionality in this patch! Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NJohn Rigby <john.rigby@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-11-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-5-git-send-email-john.rigby@linaro.org [PMM: * provide no-op versions of a64 functions ifndef TARGET_AARCH64; this lets us avoid #ifdefs in translate.c * insert the missing call to disas_a64_insn() * stash the insn in the DisasContext rather than reloading it in real_unallocated_encoding() ] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alexander Graf 提交于
This patch adds all the prerequisites for AArch64 support that didn't fit into split up patches. It extends important bits in the core cpu headers to also take AArch64 mode into account. Add new ARM_TBFLAG_AARCH64_STATE translation buffer flag indicate an ARMv8 cpu running in aarch64 mode vs aarch32 mode. Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NJohn Rigby <john.rigby@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-10-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-4-git-send-email-john.rigby@linaro.org [PMM: * rearranged tbflags so AArch64? is bit 31 and if it is set then 30..0 are freely available for whatever makes most sense for that mode * added version bump since we change VFP migration state * added a comment about how VFP/Neon register state works * physical address space is 48 bits, not 64 * added ARM_FEATURE_AARCH64 flag to identify 64-bit capable CPUs ] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
If we're building aarch64-linux-user then the 32 bit CPUs are all unwanted, because they can't possibly execute the 64 bit binaries we will be running; disable them. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-9-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Create a new AArch64CPU class; all 64-bit capable ARM CPUs are subclasses of this. (Currently we only support one, the "any" CPU used by linux-user.) Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-8-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
We want gen_set_pc_im() to work for both AArch64 and AArch32, but to do this we'll need the DisasContext* so we can tell which mode we're in, so pass it in as a parameter. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-7-git-send-email-peter.maydell@linaro.org
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由 Alexander Graf 提交于
Correct a few places that were using uint32_t or a 32 bit only format string to handle something that should be a target_ulong. Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NJohn Rigby <john.rigby@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-6-git-send-email-peter.maydell@linaro.org [PMM: split out to separate patch; added gen_goto_tb() and gen_set_pc_im() dest params to list of things to change.] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alexander Graf 提交于
The cpu_env tcg variable will be used by both the AArch32 and AArch64 handling code. Unstaticify it, so that both sides can make use of it. Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NJohn Rigby <john.rigby@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-5-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-3-git-send-email-john.rigby@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alexander Graf 提交于
We will need to share the disassembly status struct between AArch32 and AArch64 modes. So put it into a header file that both sides can use. Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NJohn Rigby <john.rigby@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-4-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-2-git-send-email-john.rigby@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
AArch32 code (ie traditional 32 bit world) expects to be able to pass a vaddr in a TCGv_i32. However when QEMU is compiled with TARGET_LONG_BITS=32 the TCG load/store functions take a TCGv_i64. Abstract out load/store with a 32 bit vaddr so we have a place to put the zero extension of the vaddr and the extension/truncation of the data value. Apart from the function definitions most of this patch is a simple s/tcg_gen_qemu_/gen_aa32_/. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-3-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The ARM EABI specifies that 64 bit integers should be 8 aligned; remove our incorrect setting of 4 alignment. This has no actual effect since it only set the alignment for the 'abi_ullong' and 'abi_llong' types, which are used only inside code which is MIPS-specific, but it will avoid problems later if we use the types elsewhere. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Clarify a comment about the ID register value presented by the PL110 variant present on the VersatilePB board (based on testing what the actual hardware does), to indicate that this is not an error in our emulation, and to remove an #if-0. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cole Robinson 提交于
Libvirt uses this to introspect available CPU models. Signed-off-by: NCole Robinson <crobinso@redhat.com> Reviewed-by: NAndreas Färber <afaerber@suse.de> Message-id: c0bdcd6c7ea6a085a6902ccaa73180fd771c8267.1378303555.git.crobinso@redhat.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Sebastian Ottlik 提交于
When the initial SP is loaded from the vector table on ARMv7M systems the two least significant bits are ignored as the stack is always aligned at a four byte boundary (see ARM DDI 0403C, B1.4.1 and B1.5.5). So far QEMU did not ignore these bits leading to a stack alignment inconsitent with real hardware for binaries that rely on this behaviour. This patch fixes this issue by masking the two least significant bits when loading the SP. Signed-off-by: NSebastian Ottlik <ottlik@fzi.de> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378286595-27072-1-git-send-email-ottlik@fzi.de Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Avoid the undefined behaviour of "1 << 31" by using 1U to make the shift be of an unsigned value rather than shifting into the sign bit of a signed integer. For consistency, we make all the CPSR_* constants unsigned, though the only one which triggers undefined behaviour is CPSR_N. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net> Message-id: 1378391908-22137-3-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
In the decode of ARM B and BL insns, swap the order of the "append 2 implicit zeros to imm24" and the sign extend, and use the new sextract32() utility function to do the latter. This avoids a direct dependency on the undefined C behaviour of shifting into the sign bit of an integer. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net> Message-id: 1378391908-22137-2-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Make the 'any' CPU for target-arm available only in linux-user mode. The ARM target provides a CPU named "any", which turns on support for all user-level instruction set extensions we know about. This is intended for linux-user emulation mode, where it is the default CPU type. It makes no sense to try to use this for system emulation, since we don't initialize it with any system-level information like feature register values or implementation specific cp15 registers. (Unsurprisingly, some boards won't boot at all, though you might get lucky in some cases where the guest doesn't happen to prod things that aren't there.) Prevent users from making this command line error by removing the CPU definition from the softmmu build. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAndreas Färber <afaerber@suse.de> Message-id: 1378213995-12945-1-git-send-email-peter.maydell@linaro.org
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- 10 9月, 2013 1 次提交
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由 Paul Burton 提交于
A Malta board can support up to 2GiB of RAM. Since the unmapped kseg0/1 regions are only 512MiB large & the latter 256MiB of those are taken up by the IO region, access to RAM beyond 256MiB must be done through a mapped region. In the case of a Linux guest this means we need to use highmem. The mainline Linux kernel does not support highmem for Malta at this time, however this can be tested using the linux-mti-3.8 kernel branch available from: git://git.linux-mips.org/pub/scm/linux-mti.git You should be able to boot a Linux kernel built from the linux-mti-3.8 branch, with CONFIG_HIGHMEM enabled, using 2GiB RAM by passing "-m 2G" to QEMU and appending the following kernel parameters: mem=256m@0x0 mem=256m@0x90000000 mem=1536m@0x20000000 Note that the upper half of the physical address space of a Malta mirrors the lower half (hence the 2GiB limit) except that the IO region (0x10000000-0x1fffffff in the lower half) is not mirrored in the upper half. That is, physical addresses 0x90000000-0x9fffffff access RAM rather than the IO region, resulting in a physical address space resembling the following: 0x00000000 -> 0x0fffffff RAM 0x10000000 -> 0x1fffffff I/O 0x20000000 -> 0x7fffffff RAM 0x80000000 -> 0x8fffffff RAM (mirror of 0x00000000 -> 0x0fffffff) 0x90000000 -> 0x9fffffff RAM 0xa0000000 -> 0xffffffff RAM (mirror of 0x20000000 -> 0x7fffffff) The second mem parameter provided to the kernel above accesses the second 256MiB of RAM through the upper half of the physical address space, making use of the aliasing described above in order to avoid the IO region and use the whole 2GiB RAM. The memory setup may be seen as 'backwards' in this commit since the 'real' memory is mapped in the upper half of the physical address space and the lower half contains the aliases. On real hardware it would be typical to see the upper half of the physical address space as the alias since the bus addresses generated match the lower half of the physical address space. However since the memory accessible in the upper half of the physical address space is uninterrupted by the IO region it is easiest to map the RAM as a whole there, and functionally it makes no difference to the target code. Due to the requirements of accessing the second 256MiB of RAM through a mapping to the upper half of the physical address space it is usual for the bootloader to indicate a maximum of 256MiB memory to a kernel. This allows kernels which do not support such access to boot on systems with more than 256MiB of RAM. It is also the behaviour assumed by Linux. QEMUs small generated bootloader is modified to provide this behaviour. Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 06 9月, 2013 6 次提交
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由 Anthony Liguori 提交于
# By Jan Kiszka (2) and others # Via Paolo Bonzini * bonzini/iommu-for-anthony: exec: do tcg_commit only when tcg_enabled Revert "memory: Return -1 again on reads from unsigned regions" memory: Provide separate handling of unassigned io ports accesses exec: check offset_within_address_space for register subpage exec: fix writing to MMIO area with non-power-of-two length Message-id: 1378401455-583-1-git-send-email-pbonzini@redhat.com
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由 liguang 提交于
Signed-off-by: Nliguang <lig.fnst@cn.fujitsu.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Jan Kiszka 提交于
This reverts commit 9b8c6924. The commit was wrong: We only return -1 on invalid accesses, not on valid but unbacked ones. This broke various corner cases. Cc: qemu-stable@nongnu.org Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Jan Kiszka 提交于
Accesses to unassigned io ports shall return -1 on read and be ignored on write. Ensure these properties via dedicated ops, decoupling us from the memory core's handling of unassigned accesses. Cc: qemu-stable@nongnu.org Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Hu Tao 提交于
If offset_within_address_space falls in a page, then we register a subpage. So check offset_within_address_space rather than offset_within_region. Cc: qemu-stable@nongnu.org Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Richard Henderson <rth@twiddle.net> Cc: "Andreas Färber" <afaerber@suse.de> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: NHu Tao <hutao@cn.fujitsu.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
The problem is introduced by commit 23326164 (exec: Support 64-bit operations in address_space_rw, 2013-07-08). Before that commit, memory_access_size would only return 1/2/4. Since alignment is already handled above, reduce l to the largest power of two that is smaller than l. Cc: qemu-stable@nongnu.org Reported-by: NOleksii Shevchuk <alxchk@gmail.com> Tested-by: NOleksii Shevchuk <alxchk@gmail.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 05 9月, 2013 1 次提交
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由 Anthony Liguori 提交于
This makes get_maintainers.pl behave a little better. Reported-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAnthony Liguori <anthony@codemonkey.ws>
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- 04 9月, 2013 5 次提交
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由 Anthony Liguori 提交于
QOM CPUState refactorings / X86CPU * Conversion of global CPU list to QTAILQ - preparing for CPU hot-unplug * Document X86CPU magic numbers for CPUID cache info # gpg: Signature made Tue 03 Sep 2013 10:59:22 AM CDT using RSA key ID 3E7E013F # gpg: Can't check signature: public key not found # By Andreas Färber (3) and Eduardo Habkost (1) # Via Andreas Färber * afaerber/tags/qom-cpu-for-anthony: target-i386: Use #defines instead of magic numbers for CPUID cache info cpu: Replace qemu_for_each_cpu() cpu: Use QTAILQ for CPU list a15mpcore: Use qemu_get_cpu() for generic timers
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由 Anthony Liguori 提交于
# By Max Reitz (11) and others # Via Kevin Wolf * kwolf/for-anthony: (26 commits) qemu-iotests: Overlapping cluster allocations qcow2_check: Mark image consistent qcow2-refcount: Repair shared refcount blocks qcow2-refcount: Repair OFLAG_COPIED errors qcow2-refcount: Move OFLAG_COPIED checks qcow2: Employ metadata overlap checks qcow2: Metadata overlap checks qcow2: Add corrupt bit qemu-iotests: Snapshotting zero clusters qcow2-refcount: Snapshot update for zero clusters option: Add assigned flag to QEMUOptionParameter gluster: Abort on AIO completion failure block: Remove old raw driver switch raw block driver from "raw.o" to "raw_bsd.o" raw_bsd: register bdrv_raw raw_bsd: add raw_create_options raw_bsd: introduce "special members" raw_bsd: add raw_create() raw_bsd: emit debug events in bdrv_co_readv() and bdrv_co_writev() add skeleton for BSD licensed "raw" BlockDriver ... Message-id: 1378111792-20436-1-git-send-email-kwolf@redhat.com Signed-off-by: NAnthony Liguori <anthony@codemonkey.ws>
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由 Anthony Liguori 提交于
# By Stefan Weil (6) and others # Via Michael Tokarev * mjt/trivial-patches: aio / timers: use g_usleep() not sleep() adlib: sort offsets in portio registration qmp: fix integer usage in examples tci: Remove function tcg_out64 (fix broken build) target-arm: Report unimplemented opcodes (LOG_UNIMP) pflash_cfi02.c: fix debug macro configure: Remove unneeded redirections of stderr (pkg-config --exists) configure: Remove unneeded redirections of stderr (pkg-config --cflags, --libs) configure: Don't write .pyc files by default (python -B) curl: qemu_bh_new() can never return NULL slirp/arp_table.c: Avoid shifting into sign bit of signed integers configure: disable clang -Wstring-plus-int warning rdma: silly ipv6 bugfix misc: Fix some typos in names and comments slirp: Port redirection option behave differently on Linux and Windows Message-id: 1378119695-14568-1-git-send-email-mjt@msgid.tls.msk.ru Signed-off-by: NAnthony Liguori <anthony@codemonkey.ws>
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由 Anthony Liguori 提交于
# By Gerd Hoffmann (10) and Marcel Apfelbaum (1) # Via Gerd Hoffmann * kraxel/usb.88: usb/dev-hid: Modified usb-tablet category from Misc to Input Revert "usb-hub: report status changes only once" usb-hub: add tracepoint for status reports usb: parallelize usb3 streams uas: add property for request logging xhci: reset port when disabling slot xhci: emulate intr endpoint intervals correctly xhci: fix endpoint interval calculation xhci: add port to slot_address tracepoint xhci: add tracepoint for endpoint state changes xhci: remove leftover debug printf Message-id: 1378117055-29620-1-git-send-email-kraxel@redhat.com Signed-off-by: NAnthony Liguori <anthony@codemonkey.ws>
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由 Anthony Liguori 提交于
pc,pci,virtio fixes and cleanups This includes pc and pci cleanups and enhancements, and a virtio bugfix for level interrupts. Signed-off-by: NMichael S. Tsirkin <mst@redhat.com> # gpg: Signature made Sun 01 Sep 2013 03:15:36 AM CDT using RSA key ID D28D5469 # gpg: Can't check signature: public key not found # By Michael S. Tsirkin (3) and others # Via Michael S. Tsirkin * mst/tags/for_anthony: virtio_pci: fix level interrupts with irqfd pc: reduce duplication, fix PIIX descriptions hw: Clean up bogus default boot order pci: add config space access traces pc: fix regression for 64 bit PCI memory pci: Introduce helper to retrieve a PCI device's DMA address space Message-id: 1378023590-11109-1-git-send-email-mst@redhat.com Signed-off-by: NAnthony Liguori <anthony@codemonkey.ws>
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