1. 22 3月, 2013 23 次提交
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      mmu-hash*: Reduce use of access_type · 91cda45b
      David Gibson 提交于
      In ppc env->access_type is updated by e.g. integer load/stores with
      ACCESS_INT floating point load/stores with ACCESS_FLOAT and so forth.  In
      hash mmu fault paths it can also b set to ACCESS_CODE for instruction
      fetch accesses.
      
      But the only place which uses anything more of the access_type than
      whether it is instruction fetch or data access is the direct store segment
      handling.  Instruction versus data access can be more simply determined
      from the rw value passed down from the top.
      
      This changes the code to use rw in preference to checking access_type.
      For the 32-bit case there is a small amount of code (for direct store
      segments) that still needs the full access type.  Instead of passing it
      all the way down the stack, we retrieve it from the env structure, which
      is where it came anyway, before this patch.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      91cda45b
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      mmu-hash*: Add hash pte load/store helpers · dffdaf61
      David Gibson 提交于
      On real hardware the ppc hash page table is stored in memory; accordingly
      our mmu emulation code can read a hash page table in guest memory.  But,
      when paravirtualized under PAPR, the real hash page table is in host
      memory, accessible to the guest only via hypercalls.  We model this by
      also allowing the MMU emulation code to access a specially allocated hash
      page table outside the guest's memory image. At present these two options
      are implemented with some ugly conditionals at each access point in the mmu
      emulation code.  In the implementation of the PAPR hypercalls, we assume
      the external hash table.
      
      This patch cleans things up by adding helpers to load and store from the
      hash table for both 32-bit and 64-bit hash mmus.  The 64-bit versions
      handle both the in-guest-memory and outside guest memory cases.  The 32-bit
      versions only handle the in-guest-memory case since no 32-bit systems can
      have an external hash table at present.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      dffdaf61
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      mmu-hash*: Add header file for definitions · d5aea6f3
      David Gibson 提交于
      Currently cpu.h contains a number of definitions relating to the 64-bit
      hash MMU.  Some are used in the MMU emulation code, but some are only used
      in the spapr MMU management hcall implementations.
      
      This patch moves these definitions (except for a few that are needed
      more widely) into mmu-hash64.h header, shared between the MMU emulation
      code and the spapr hcall code.  The MMU emulation code is also updated to
      actually use a number of those definitions in place of hard coded
      constants.
      
      Similarly, we add new analogous definitions to mmu-hash32.h and use those
      in place of many hard-coded constants in mmu-hash32.c
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      [agraf: fix 32-bit hosts]
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      d5aea6f3
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      target-ppc: mmu_ctx_t should not be a global type · 5dc68eb0
      David Gibson 提交于
      mmu_ctx_t is currently defined in cpu.h.  However it is used for temporary
      information relating to mmu translation, and is only used in mmu_helper.c
      and (now) mmu-hash{32,64}.c.  Furthermore it contains information which
      should be specific to particular MMU types.  Therefore, move its definition
      to mmu_helper.c.  mmu-hash{32,64}.c are converted to use new data types
      private to the relevant MMUs (identical to mmu_ctx_t for now, but that will
      change in future patches).
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      5dc68eb0
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      target-ppc: Disentangle BAT code for 32-bit hash MMUs · 98132796
      David Gibson 提交于
      The functions for looking up BATs (Block Address Translation - essentially
      a level 0 TLB) are shared between the classic 32-bit hash MMUs and the
      6xx style software loaded TLB implementations.
      
      This patch splits out a copy for the 32-bit hash MMUs, to facilitate
      cleaning it up.  The remaining version is left, but cleaned up slightly
      to no longer deal with PowerPC 601 peculiarities (601 has a hash MMU).
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      98132796
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      target-ppc: Don't share get_pteg_offset() between 32 and 64-bit · 59191721
      David Gibson 提交于
      The get_pteg_offset() helper function is currently shared between 32-bit
      and 64-bit hash mmus, taking a parameter for the hash pte size.  In the
      64-bit paths, it's only called in one place, and it's a trivial
      calculation.  This patch, therefore, open codes it for 64-bit.  The
      remaining version, which is used in two places is made 32-bit only and
      moved to mmu-hash32.c.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      59191721
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      target-ppc: Disentangle hash mmu helper functions · 496272a7
      David Gibson 提交于
      The newly separated paths for hash mmus rely on several helper functions
      which are still shared with 32-bit hash mmus: pp_check(), check_prot() and
      pte_update_flags().  While these don't have ugly ifdefs on the mmu type,
      they're not very well thought out, so sharing them impedes cleaning up the
      hash mmu paths.  For now, put near-duplicate versions into mmu-hash64.c and
      mmu-hash32.c, leaving the old version in mmu_helper.c for 6xx software
      loaded tlb implementations.  The hash 32 and software loaded
      implementations are simplfied slightly, using the fact that no 32-bit CPUs
      implement the 3rd page protection bit.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      496272a7
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      target-ppc: Disentangle hash mmu versions of cpu_get_phys_page_debug() · f2ad6be8
      David Gibson 提交于
      cpu_get_phys_page_debug() is a trivial wrapper around
      get_physical_address().  But even the signature of
      get_physical_address() has some things we'd like to clean up on a
      per-mmu basis, so this patch moves the test on mmu model out to
      cpu_get_phys_page_debug(), moving the version for 64-bit hash MMUs out
      to mmu-hash64.c and the version for 32-bit hash MMUs to mmu-hash32.c
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      f2ad6be8
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      target-ppc: Disentangle hash mmu paths for cpu_ppc_handle_mmu_fault · 25de24ab
      David Gibson 提交于
      cpu_ppc_handle_mmu_fault() calls get_physical_address() (whose behaviour
      depends on MMU type) then, if that fails, issues an appropriate exception
      - which again has a number of dependencies on MMU type.
      
      This patch starts converting cpu_ppc_handle_mmu_fault() to have a
      single switch on MMU type, calling MMU specific fault handler
      functions which deal with both translation and exception delivery
      appropriately for the MMU type.  We convert 32-bit and 64-bit hash
      MMUs to this new model, but the existing code is left in place for
      other MMU types for now.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      25de24ab
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      target-ppc: Disentangle get_physical_address() paths · 629bd516
      David Gibson 提交于
      Depending on the MSR state, for 64-bit hash MMUs, get_physical_address
      can either call check_physical (which has further tests for mmu type)
      or get_segment64.  Similarly for 32-bit hash MMUs we can either call
      check_physucal or get_bat() and get_segment32().
      
      This patch splits off the whole get_physical_addresss() path for hash
      MMUs into 32-bit and 64-bit versions, handling real mode correctly for
      such MMUs without going to check_physical and rechecking the mmu type.
      Correspondingly, the hash MMU specific paths in check_physical() are
      removed.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      629bd516
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      target-ppc: Rework get_physical_address() · 44bc9107
      David Gibson 提交于
      Currently get_physical_address() first checks to see if translation is
      enabled in the MSR, then in the translation on case switches on the mmu
      type.  Except that for BookE MMUs, translation is always on, and so it
      has to switch in the "translation off" case as well and do the same thing
      as the translation on path for those MMUs.  Plus, even translation off
      doesn't behave exactly the same on the various MMU types so there are
      further mmu type checks in the "translation off" path.
      
      As a first step to cleaning this up, this patch moves the switch on mmu
      type to the top level, then makes the translation on/off check just for
      those mmu types where it is meaningful.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      44bc9107
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      target-ppc: Disentangle get_segment() · 0480884f
      David Gibson 提交于
      The poorly named get_segment() function handles most of the address
      translation logic for hash-based MMUs.  It has many ugly conditionals on
      whether the MMU is 32-bit or 64-bit.
      
      This patch splits the function into 32 and 64-bit versions, using the
      switch on mmu_type that's already in the caller
      (get_physical_address()) to select the right one.  Most of the
      original function remains in mmu_helper.c to support the 6xx software
      loaded TLB implementations (cleaning those up is a project for another
      day).
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      0480884f
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      target-ppc: Disentangle find_pte() · c69b6151
      David Gibson 提交于
      32-bit and 64-bit hash MMU implementations currently share a find_pte
      function.  This results in a whole bunch of ugly conditionals in the shared
      function, and not all that much actually shared code.
      
      This patch separates out the 32-bit and 64-bit versions, putting then
      in mmu-hash64.c and mmu-has32.c, and removes the conditionals from
      both versions.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      c69b6151
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      target-ppc: Disentangle pte_check() · 9d7c3f4a
      David Gibson 提交于
      Currently support for both 32-bit and 64-bit hash MMUs share an
      implementation of pte_check.  But there are enough differences that this
      means the shared function has several very ugly conditionals on "is_64b".
      
      This patch cleans things up by separating out the 64-bit version
      (putting it into mmu-hash64.c) and the 32-bit hash version (putting it
      in mmu-hash32.c).  Another copy remains in mmu_helper.c, which is used
      for the 6xx software loaded TLB paths.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      9d7c3f4a
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      target-ppc: Move SLB handling into a mmu-hash64.c · 10b46525
      David Gibson 提交于
      As a first step to disentangling the handling for 64-bit hash MMUs from
      the rest, we move the code handling the Segment Lookaside Buffer (SLB)
      (which only exists on 64-bit hash MMUs) into a new mmu-hash64.c file.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      10b46525
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      target-ppc: Remove address check for logging · 8152ceaf
      David Gibson 提交于
      One LOG_MMU statement in mmu_helper.c has an odd check on the effective
      address being translated.  I can see no reason for this; I suspect it was
      a debugging hack from long ago.  This patch removes it.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      8152ceaf
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      target-ppc: Trivial cleanups in mmu_helper.c · 213c7180
      David Gibson 提交于
      This removes the never-used pte64_invalidate() function, and makes
      ppcmas_tlb_check() static, since it's only used within that file.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      213c7180
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      target-ppc: Remove vestigial PowerPC 620 support · 9baea4a3
      David Gibson 提交于
      The PowerPC 620 was the very first 64-bit PowerPC implementation, but
      hardly anyone ever actually used the chips.  qemu notionally supports the
      620, but since we don't actually have code to implement the segment table,
      the support is broken (quite likely in other ways too).
      
      This patch, therefore, removes all remaining pieces of 620 support, to
      stop it cluttering up the platforms we actually care about.  This includes
      removing support for the ASR register, used only on segment table based
      machines.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      9baea4a3
    • F
      PPC/GDB: handle read and write of fpscr · d6478bc7
      Fabien Chouteau 提交于
      Although the support of this register may be uncomplete, there are no
      reason to prevent the debugger from reading or writing it.
      Signed-off-by: NFabien Chouteau <chouteau@adacore.com>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      d6478bc7
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      pseries: Move XICS initialization before cpu initialization · 7b565160
      David Gibson 提交于
      Currently, the pseries machine initializes the cpus, then the XICS
      interrupt controller.  However, to support the upcoming in-kernel XICS
      implementation we will need to initialize the irq controller before the
      vcpus.  This patch makes the necesssary rearrangement.  This means the
      xics init code can no longer auto-detect the number of cpus ("interrupt
      servers" in XICS terminology) and so we must pass that in explicitly from
      the platform code.
      Signed-off-by: NMichael Ellerman <michael@ellerman.id.au>
      Signed-off-by: NBen Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      7b565160
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      target-ppc: Remove CONFIG_PSERIES dependency in kvm.c · c6304a4a
      David Gibson 提交于
      target-ppc/kvm.c has an #ifdef on CONFIG_PSERIES, for the handling of
      KVM exits due to a PAPR hypercall from the guest.  However, since commit
      e4c8b28c "ppc: express FDT dependency of
      pSeries and e500 boards via default-configs/", this hasn't worked properly.
      That patch altered the configuration setup so that although CONFIG_PSERIES
      is visible from the Makefiles, it is not visible from C files.  This broke
      the pseries machine when KVM is in use.
      
      This patch makes a quick and dirty fix, by removing the CONFIG_PSERIES
      dependency, replacing it with TARGET_PPC64 (since removing it entirely
      leads to type mismatch errors).  Technically this breaks the build when
      configured with --disable-fdt, since that disables CONFIG_PSERIES on
      TARGET_PPC64.  However, it turns out the build was already broken in that
      case, so this fixes pseries kvm without breaking anything extra.  I'm
      looking into how to fix that build breakage, but I don't think that need
      delay applying this patch.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      c6304a4a
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      pseries: Remove "busname" property for PCI host bridge · 89dfd6e1
      David Gibson 提交于
      Currently the "spapr-pci-host-bridge" device has a "busname" property which
      can be used to override the default assignment of qbus names for the bus
      subordinate to the PHB.  We use that for the default primary PCI bus, to
      make libvirt happy, which expects there to be a bus named simply "pci".
      The default qdev core logic would name the bus "pci.0", and the pseries
      code would otherwise name it "pci@800000020000000" which is the name it
      is given in the device tree based on its BUID.
      
      The "busname" property is rather clunky though, so this patch simplifies
      things by just using a special case hack for the default PHB, setting
      busname to "pci" when index=0.
      Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru>
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      89dfd6e1
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      pseries: Fix breakage in CPU QOM conversion · a4e044c3
      David Gibson 提交于
      Commit 259186a7 "cpu: Move halted and
      interrupt_request fields to CPUState" broke the pseries machine.  That's
      because it uses CPU() instead of ENV_GET_CPU() to convert from the global
      first_cpu pointer (still a CPUArchState) to a CPUState.  This patch fixes
      the breakage.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      a4e044c3
  2. 20 3月, 2013 1 次提交
  3. 19 3月, 2013 16 次提交