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  1. 09 2月, 2018 1 次提交
  3. 26 1月, 2018 2 次提交
  5. 14 12月, 2017 1 次提交
  7. 21 9月, 2017 5 次提交
    • P
      nvic: Implement NVIC_ITNS<n> registers · e1be0a57
      由 Peter Maydell 提交于 
      For v8M, the NVIC has a new set of registers per interrupt,
NVIC_ITNS<n>. These determine whether the interrupt targets Secure
or Non-secure state. Implement the register read/write code for
these, and make them cause NVIC_IABR, NVIC_ICER, NVIC_ISER,
NVIC_ICPR, NVIC_IPR and NVIC_ISPR to RAZ/WI for non-secure
accesses to fields corresponding to interrupts which are
configured to target secure state.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 1505240046-11454-8-git-send-email-peter.maydell@linaro.org
      e1be0a57
    • P
      nvic: Implement AIRCR changes for v8M · 3b2e9344
      由 Peter Maydell 提交于 
      The Application Interrupt and Reset Control Register has some changes
for v8M:
 * new bits SYSRESETREQS, BFHFNMINS and PRIS: these all have
   real state if the security extension is implemented and otherwise
   are constant
 * the PRIGROUP field is banked between security states
 * non-secure code can be blocked from using the SYSRESET bit
   to reset the system if SYSRESETREQS is set

Implement the new state and the changes to register read and write.
For the moment we ignore the effects of the secure PRIGROUP.
We will implement the effects of PRIS and BFHFNMIS later.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 1505240046-11454-6-git-send-email-peter.maydell@linaro.org
      3b2e9344
    • P
      nvic: Add cached vectpending_prio state · 5255fcf8
      由 Peter Maydell 提交于 
      Instead of looking up the pending priority
in nvic_pending_prio(), cache it in a new state struct
field. The calculation of the pending priority given
the interrupt number is more complicated in v8M with
the security extension, so the caching will be worthwhile.

This changes nvic_pending_prio() from returning a full
(group + subpriority) priority value to returning a group
priority. This doesn't require changes to its callsites
because we use it only in comparisons of the form
  execution_prio > nvic_pending_prio()
and execution priority is always a group priority, so
a test (exec prio > full prio) is true if and only if
(execprio > group_prio).

(Architecturally the expected comparison is with the
group priority for this sort of "would we preempt" test;
we were only doing a test with a full priority as an
optimisation to avoid the mask, which is possible
precisely because the two comparisons always give the
same answer.)
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-id: 1505240046-11454-5-git-send-email-peter.maydell@linaro.org
      5255fcf8
    • P
      nvic: Add cached vectpending_is_s_banked state · e93bc2ac
      由 Peter Maydell 提交于 
      With banked exceptions, just the exception number in
s->vectpending is no longer sufficient to uniquely identify
the pending exception. Add a vectpending_is_s_banked bool
which is true if the exception is using the sec_vectors[]
array.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1505240046-11454-4-git-send-email-peter.maydell@linaro.org
      e93bc2ac
    • P
      nvic: Add banked exception states · 17906a16
      由 Peter Maydell 提交于 
      For the v8M security extension, some exceptions must be banked
between security states. Add the new vecinfo array which holds
the state for the banked exceptions and migrate it if the
CPU the NVIC is attached to implements the security extension.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
      17906a16
  9. 07 9月, 2017 1 次提交
    • P
      nvic: Add NS alias SCS region · f104919d
      由 Peter Maydell 提交于 
      For v8M the range 0xe002e000..0xe002efff is an alias region which
for secure accesses behaves like a NonSecure access to the main
SCS region. (For nonsecure accesses including when the security
extension is not implemented, it is RAZ/WI.)
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1503414539-28762-11-git-send-email-peter.maydell@linaro.org
      f104919d
  11. 04 9月, 2017 1 次提交
  13. 13 6月, 2017 1 次提交
    • E
      hw/intc/arm_gicv3_its: Implement state save/restore · cddafd8f
      由 Eric Auger 提交于 
      We need to handle both registers and ITS tables. While
register handling is standard, ITS table handling is more
challenging since the kernel API is devised so that the
tables are flushed into guest RAM and not in vmstate buffers.

Flushing the ITS tables on device pre_save() is too late
since the guest RAM is already saved at this point.

Table flushing needs to happen when we are sure the vcpus
are stopped and before the last dirty page saving. The
right point is RUN_STATE_FINISH_MIGRATE but sometimes the
VM gets stopped before migration launch so let's simply
flush the tables each time the VM gets stopped.

For regular ITS registers we just can use vmstate pre_save()
and post_load() callbacks.
Signed-off-by: NEric Auger <eric.auger@redhat.com>
Message-id: 1497023553-18411-3-git-send-email-eric.auger@redhat.com
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      cddafd8f
  15. 01 3月, 2017 1 次提交
  17. 20 1月, 2017 4 次提交
  19. 04 10月, 2016 2 次提交
  21. 14 7月, 2016 1 次提交
  23. 12 7月, 2016 3 次提交
  25. 17 6月, 2016 4 次提交
  27. 17 3月, 2016 1 次提交
  29. 03 2月, 2016 2 次提交
  31. 27 10月, 2015 1 次提交
  33. 24 9月, 2015 1 次提交
  35. 09 9月, 2015 3 次提交
  37. 13 8月, 2015 2 次提交
  39. 12 5月, 2015 3 次提交