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  1. 17 6月, 2019 8 次提交
  3. 14 6月, 2019 23 次提交
  5. 13 6月, 2019 9 次提交
    • E
      vfio/common: Introduce vfio_set_irq_signaling helper · 201a7331
      由 Eric Auger 提交于 
      The code used to assign an interrupt index/subindex to an
eventfd is duplicated many times. Let's introduce an helper that
allows to set/unset the signaling for an ACTION_TRIGGER,
ACTION_MASK or ACTION_UNMASK action.

In the error message, we now use errno in case of any
VFIO_DEVICE_SET_IRQS ioctl failure.
Signed-off-by: NEric Auger <eric.auger@redhat.com>
Reviewed-by: NCornelia Huck <cohuck@redhat.com>
Reviewed-by: NLi Qiang <liq3ea@gmail.com>
Signed-off-by: NAlex Williamson <alex.williamson@redhat.com>
      201a7331
    • A
      vfio/pci: Allow MSI-X relocation to fixup bogus PBA · c60807de
      由 Alex Williamson 提交于 
      The MSI-X relocation code can sometimes be used to work around bogus
MSI-X capabilities, but this test for whether the PBA is outside of
the specified BAR causes the device to error before we can apply a
relocation.  Let it proceed if we intend to relocate MSI-X anyway.
Signed-off-by: NAlex Williamson <alex.williamson@redhat.com>
      c60807de
    • A
      vfio/pci: Hide Resizable BAR capability · 3412d8ec
      由 Alex Williamson 提交于 
      The resizable BAR capability is currently exposed read-only from the
kernel and we don't yet implement a protocol for virtualizing it to
the VM.  Exposing it to the guest read-only introduces poor behavior
as the guest has no reason to test that a control register write is
accepted by the hardware.  This can lead to cases where the guest OS
assumes the BAR has been resized, but it hasn't.  This has been
observed when assigning AMD Vega GPUs.

Note, this does not preclude future enablement of resizable BARs, but
it's currently incorrect to expose this capability as read-only, so
better to not expose it at all.
Reported-by: NJames Courtier-Dutton <james.dutton@gmail.com>
Tested-by: NJames Courtier-Dutton <james.dutton@gmail.com>
Signed-off-by: NAlex Williamson <alex.williamson@redhat.com>
      3412d8ec
    • V
      block/nbd: merge NBDClientSession struct back to BDRVNBDState · 611ae1d7
      由 Vladimir Sementsov-Ogievskiy 提交于 
      No reason to keep it separate, it differs from others block driver
behavior and therefore confuses. Instead of generic
  'state = (State*)bs->opaque' we have to use special helper.
Signed-off-by: NVladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20190611102720.86114-4-vsementsov@virtuozzo.com>
Reviewed-by: NEric Blake <eblake@redhat.com>
Signed-off-by: NEric Blake <eblake@redhat.com>
      611ae1d7
    • V
      block/nbd: merge nbd-client.* to nbd.c · 86f8cdf3
      由 Vladimir Sementsov-Ogievskiy 提交于 
      No reason for keeping driver handlers realization separate from driver
structure. We can get rid of extra header file.

While being here, fix comments style, restore forgotten comments for
NBD_FOREACH_REPLY_CHUNK and nbd_reply_chunk_iter_receive, remove extra
includes.
Signed-off-by: NVladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20190611102720.86114-3-vsementsov@virtuozzo.com>
Reviewed-by: NEric Blake <eblake@redhat.com>
Signed-off-by: NEric Blake <eblake@redhat.com>
      86f8cdf3
    • V
      block/nbd-client: drop stale logout · 0a93b359
      由 Vladimir Sementsov-Ogievskiy 提交于 
      Drop one on failure path (we have errp) and turn two others into trace
points.
Signed-off-by: NVladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20190611102720.86114-2-vsementsov@virtuozzo.com>
Reviewed-by: NEric Blake <eblake@redhat.com>
Signed-off-by: NEric Blake <eblake@redhat.com>
      0a93b359
    • P
      Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190613-1' into staging · 650a379d
      由 Peter Maydell 提交于 
      target-arm queue:
 * convert aarch32 VFP decoder to decodetree
   (includes tightening up decode in a few places)
 * fix minor bugs in VFP short-vector handling
 * hw/core/bus.c: Only the main system bus can have no parent
 * smmuv3: Fix decoding of ID register range
 * Implement NSACR gating of floating point
 * Use tcg_gen_gvec_bitsel

# gpg: Signature made Thu 13 Jun 2019 15:15:39 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20190613-1: (47 commits)
  target/arm: Fix short-vector increment behaviour
  target/arm: Convert float-to-integer VCVT insns to decodetree
  target/arm: Convert VCVT fp/fixed-point conversion insns to decodetree
  target/arm: Convert VJCVT to decodetree
  target/arm: Convert integer-to-float insns to decodetree
  target/arm: Convert double-single precision conversion insns to decodetree
  target/arm: Convert VFP round insns to decodetree
  target/arm: Convert the VCVT-to-f16 insns to decodetree
  target/arm: Convert the VCVT-from-f16 insns to decodetree
  target/arm: Convert VFP comparison insns to decodetree
  target/arm: Convert VMOV (register) to decodetree
  target/arm: Convert VSQRT to decodetree
  target/arm: Convert VNEG to decodetree
  target/arm: Convert VABS to decodetree
  target/arm: Convert VMOV (imm) to decodetree
  target/arm: Convert VFP fused multiply-add insns to decodetree
  target/arm: Convert VDIV to decodetree
  target/arm: Convert VSUB to decodetree
  target/arm: Convert VADD to decodetree
  target/arm: Convert VNMUL to decodetree
  ...
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      650a379d
    • P
      target/arm: Fix short-vector increment behaviour · 18cf951a
      由 Peter Maydell 提交于 
      For VFP short vectors, the VFP registers are divided into a
series of banks: for single-precision these are s0-s7, s8-s15,
s16-s23 and s24-s31; for double-precision they are d0-d3,
d4-d7, ... d28-d31. Some banks are "scalar" meaning that
use of a register within them triggers a pure-scalar or
mixed vector-scalar operation rather than a full vector
operation. The scalar banks are s0-s7, d0-d3 and d16-d19.
When using a bank as part of a vector operation, we
iterate through it, increasing the register number by
the specified stride each time, and wrapping around to
the beginning of the bank.

Unfortunately our calculation of the "increment" part of this
was incorrect:
 vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask)
will only do the intended thing if bank_mask has exactly
one set high bit. For instance for doubles (bank_mask = 0xc),
if we start with vd = 6 and delta_d = 2 then vd is updated
to 12 rather than the intended 4.

This only causes problems in the unlikely case that the
starting register is not the first in its bank: if the
register number doesn't have to wrap around then the
expression happens to give the right answer.

Fix this bug by abstracting out the "check whether register
is in a scalar bank" and "advance register within bank"
operations to utility functions which use the right
bit masking operations.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
      18cf951a
    • P
      target/arm: Convert float-to-integer VCVT insns to decodetree · 3111bfc2
      由 Peter Maydell 提交于 
      Convert the float-to-integer VCVT instructions to decodetree.
Since these are the last unconverted instructions, we can
delete the old decoder structure entirely now.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
      3111bfc2