- 29 4月, 2013 5 次提交
-
-
由 Andreas Färber 提交于
Add a typedef for the state struct and rename from Status to State. Add type constant and cast macro to obsolete DO_UPCAST(). Prepares for ISA realizefn. Signed-off-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NAndreas Färber <afaerber@suse.de> Message-id: 1367093935-29091-2-git-send-email-afaerber@suse.de Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
-
由 Jason Wang 提交于
Multiqueue patchset conditionally add control vq only when guest negotiate the feature. Though the spec is not clear on this but it breaks the minix guest since it will identify the ctrl vq even if it does not support it. Though this behavior seems a violation on the spec "If the VIRTIO_NET_F_CTRL_VQ feature bit is negotiated, identify the control virtqueue.", to keep the backward compatibility, always add the ctrl vq at end of the queues. Reported-by: NAurelien Jarno <aurelien@aurel32.net> Acked-by: NMichael S. Tsirkin <mst@redhat.com> Tested-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NJason Wang <jasowang@redhat.com> Message-id: 1366874663-2566-1-git-send-email-jasowang@redhat.com Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: NJason Wang <jasowang@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
-
由 Anthony Liguori 提交于
# By Paolo Bonzini # Via Paolo Bonzini * bonzini/migration-writev: win32: add readv/writev emulation win32: generate console executable again win32: move Makefile dependencies on version-obj-y to rules.mak win32: add generic RC rules to rules.mak Message-id: 1367230284-24612-1-git-send-email-pbonzini@redhat.com Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
-
由 Anthony Liguori 提交于
# By Cole Robinson # Via Alon Levy * alon/libcacard_ccid.2: ccid: Fix crash when backend isn't specified Message-id: 20130426234357.GA12457@garlic.tami Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
-
由 Paolo Bonzini 提交于
Commit e9d8fbf5 (qemu-file: do not use stdio for qemu_fdopen, 2013-03-27) introduced a usage of writev, which mingw32 does not have. Even though qemu_fdopen itself is not used on mingw32, the future-proof solution is to add an implementation of it. This is simple and similar to how we emulate sendmsg/recvmsg in util/iov.c. Some files include osdep.h without qemu-common.h, so move the definition of iovec to osdep.h too, and include osdep.h from qemu-common.h unconditionally (protection against including files when NEED_CPU_H is defined is not needed since the removal of AREG0). Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
-
- 27 4月, 2013 35 次提交
-
-
由 Artyom Tarasenko 提交于
Every PCI Slot in PBM has 4 directly mapped IRQ lines. Use the IRQ routing schema 0bssnn (Bus, Slot, interrupt Number) described in Section 19.3.3 of UltraSPARC™-IIi User's Manual. Please note that this patch requires the OpenBIOS counterpart patch. Signed-off-by: NArtyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
-
由 Artyom Tarasenko 提交于
- clear interrupts only on writing to the interrupt clear registers - don't overwrite a currently active interrupt request - use the correct addresses for the interrupt clear registers (section 19.3.3.3 of the UltraSPARC™-IIi User’s Manual) Signed-off-by: NArtyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
-
由 Artyom Tarasenko 提交于
According to UltraSPARC™-IIi User’s Manual, PBM has 64 IRQ lines. Signed-off-by: NArtyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
-
由 Richard Henderson 提交于
Branches within a TB will always be within 16MB. Signed-off-by: NRichard Henderson <rth@twiddle.net>
-
由 Richard Henderson 提交于
Move the slow path out of line, as the TODO's mention. This allows the fast path to be unconditional, which can speed up the fast path as well, depending on the core. Signed-off-by: NRichard Henderson <rth@twiddle.net>
-
由 Richard Henderson 提交于
Work better with branch predition when we have movw+movt, as the size of the code is the same. Perhaps re-evaluate when we have a proper constant pool. Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
-
由 Richard Henderson 提交于
After the previous patch, 's' and 'S' are the same. Signed-off-by: NRichard Henderson <rth@twiddle.net>
-
由 Richard Henderson 提交于
The schedule was fully serial, with no possibility for dual issue. The old schedule had a minimal issue of 7 cycles; the new schedule has a minimal issue of 5 cycles. Signed-off-by: NRichard Henderson <rth@twiddle.net>
-
由 Richard Henderson 提交于
Share code between qemu_ld and qemu_st to process the tlb. Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
-
由 Richard Henderson 提交于
Use even more primitive helper functions to avoid lots of duplicated code. Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
-
由 Richard Henderson 提交于
Make the code more readable by only having one copy of the magic numbers, swapping registers as needed prior to that. Speed the compiler by not applying the rd == rn avoidance for v6 or later. Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
-
由 Richard Henderson 提交于
R12 is call clobbered, while R8 is call saved. This change gives tcg one more call saved register for real data. Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
-
由 Richard Henderson 提交于
Don't hard-code R8. Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
-
由 Richard Henderson 提交于
An armv7 extension implements division, present on Cortex A15. Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
-
由 Richard Henderson 提交于
We have BFI and BFC available for implementing it. Signed-off-by: NRichard Henderson <rth@twiddle.net>
-
由 Richard Henderson 提交于
Try fully rotated arguments to mov and mvn before trying movt or full decomposition. Begin decomposition with mvn when it looks like it'll help. Examples include -: mov r9, #0x00000fa0 -: orr r9, r9, #0x000ee000 -: orr r9, r9, #0x0ff00000 -: orr r9, r9, #0xf0000000 +: mvn r9, #0x0000005f +: eor r9, r9, #0x00011000 Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
-
由 Richard Henderson 提交于
We get to re-use the _rIN and _rIK subroutines to handle the various combinations of add vs sub. Fold the << 21 into the opcode enum values so that we can explicitly add TO_CPSR as desired. Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
-
由 Richard Henderson 提交于
This allows us to emit CMN instructions. Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
-
由 Richard Henderson 提交于
This allows the generation of RSB instructions. Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
-
由 Richard Henderson 提交于
This greatly improves code generation for addition of small negative constants. Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
-
由 Richard Henderson 提交于
This greatly improves the code we can produce for deposit without armv7 support. Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
-
由 Richard Henderson 提交于
This makes it easier to verify changes to the code generating the prologue. [Aurelien: change the format from %i to %zu] Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
-
由 Cole Robinson 提交于
Reproducer: ./x86_64-softmmu/qemu-system-x86_64 -device usb-ccid,id=ccid0 -usb -device ccid-card-emulated -monitor stdio Signed-off-by: NCole Robinson <crobinso@redhat.com> Reviewed-by: NAlon Levy <alevy@redhat.com>
-
由 Richard Henderson 提交于
We were not allocating TCG_STATIC_CALL_ARGS_SIZE, so this meant that any helper with more than 4 arguments would clobber the saved regs. Realizing that we're supposed to have this memory pre-allocated means we can clean up the tcg_out_arg functions, which were trying to do more stack allocation. Allocate stack memory for the TCG temporaries while we're at it. Signed-off-by: NRichard Henderson <rth@twiddle.net>
-
由 Aurelien Jarno 提交于
On 32-bit TCG targets, when emulating deposit_i64 with a mov_i32 + deposit_i32, care should be taken to not overwrite the low part of the second argument before the deposit when it is the same the destination. This fixes the shld instruction in qemu-system-x86_64, which in turns fixes booting "system rescue CD version 2.8.0" on this target. Reported-by: NMichael S. Tsirkin <mst@redhat.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
-
由 Aurelien Jarno 提交于
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
-
git://github.com/agraf/qemu由 Aurelien Jarno 提交于
* 'ppc-for-upstream' of git://github.com/agraf/qemu: (30 commits) target-ppc: add support for extended mtfsf/mtfsfi forms target-ppc: emulate store doubleword pair instructions target-ppc: emulate load doubleword pair instructions target-ppc: emulate lfiwax instruction target-ppc: emulate fcpsgn instruction target-ppc: emulate prtyw and prtyd instructions target-ppc: emulate cmpb instruction target-ppc: add instruction flags for Book I 2.05 disas: Disassemble all ppc insns for the guest target-ppc: optimize fabs, fnabs, fneg PPC: Fix dcbz for linux-user on 970 powerpc: correctly handle fpu exceptions. pseries: Generate device paths for VIO devices pseries: Convert VIO code to QOM style type safe(ish) casts target-ppc: Synchronize VPA state with KVM pseries: Fix some small errors in XICS logic target-ppc: Add more stubs for POWER7 PMU registers pseries: Fixes and enhancements to L1 cache properties pseries: Fix incorrect calculation of RMA size in certain configurations PPC: Fix compile with profiling enabled ...
-
由 Paolo Bonzini 提交于
The -mwindows option is not anymore in LIBS at this point of the Makefile, it is only in libs_softmmu. Check the right variable. Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
-
由 Paolo Bonzini 提交于
This makes the test on $(LIBTOOL) work. Otherwise, LIBTOOL is /bin/false by the time the test is done. Fixes Win32 compilation without a working cross-libtool. Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
-
由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
-
由 Aurelien Jarno 提交于
Power ISA 2.05 adds support for extended mtfsf/mtfsfi form, with a new W field to select the upper part of the FPCSR register. For that the helper is changed to handle 64-bit input values and mask with up to 16 bits. The mtfsf/mtfsfi instructions do not have the W bit marked as invalid anymore. Instead this is checked in the helper, which therefore needs to access to the insns/insns_flags2. They are added in the DisasContext struct. Finally change all accesses to the opcode fields through extract helpers, prefixed with FP for consistency. Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
-
由 Aurelien Jarno 提交于
Needed for Power ISA version 2.05 compliance. The check for odd register pairs is done using the invalid bits. Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
-
由 Aurelien Jarno 提交于
Needed for Power ISA version 2.05 compliance. The check for odd register pairs is done using the invalid bits. Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
-
由 Aurelien Jarno 提交于
Needed for Power ISA version 2.05 compliance. Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> [agraf: fix tcg debug error] Signed-off-by: NAlexander Graf <agraf@suse.de>
-
由 Aurelien Jarno 提交于
Needed for Power ISA version 2.05 compliance. Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
-