- 17 9月, 2019 40 次提交
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由 Bin Meng 提交于
Now that we have added a PRCI node, update existing UART and ethernet nodes to reference PRCI as their clock sources, to keep in sync with the Linux kernel device tree. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
Add PRCI mmio base address and size mappings to sifive_u machine, and generate the corresponding device tree node. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
To keep in sync with Linux kernel device tree, generate hfclk and rtcclk nodes in the device tree, to be referenced by PRCI node. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
This adds a simple PRCI model for FU540 (sifive_u). It has different register layout from the existing PRCI model for FE310 (sifive_e). Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
With heterogeneous harts config, the PLIC hart topology configuration string are "M,MS,.." because of the monitor hart #0. Suggested-by: NFabien Chouteau <chouteau@adacore.com> Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
The FU540-C000 includes a 64-bit E51 RISC-V core and four 64-bit U54 RISC-V cores. Currently the sifive_u machine only populates 4 U54 cores. Update the max cpu number to 5 to reflect the real hardware, by creating 2 CPU clusters as containers for RISC-V hart arrays to populate heterogeneous harts. The cpu nodes in the generated DTS have been updated as well. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
It is not useful if we only have one management CPU. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> [Palmer: Set default CPUs to 2] Reviewed-by: NPalmer Dabbelt <palmer@sifive.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
At present each hart's hartid in a RISC-V hart array is assigned the same value of its index in the hart array. But for a system that has multiple hart arrays, this is not the case any more. Add a new "hartid-base" property so that hartid number can be assigned based on the property value. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
Currently riscv_harts_realize() creates all harts based on the same cpu type given in the hart array property. With current implementation it can only create homogeneous harts. Exact the hart realize to a separate routine in preparation for supporting multiple hart arrays. Note the file header says the RISC-V hart array holds the state of a heterogeneous array of RISC-V harts, which is not true. Update the comment to mention homogeneous array of RISC-V harts. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
Group SiFive E and U cpu type defines into one header file. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
Use create_unimplemented_device() instead. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
Currently the PRCI register block size is set to 0x8000, but in fact 0x1000 is enough, which is also what the manual says. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NChih-Min Chao <chihmin.chao@sifive.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
For hfxosccfg register programming, SIFIVE_E_PRCI_HFXOSCCFG_RDY and SIFIVE_E_PRCI_HFXOSCCFG_EN should be used. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NAlistair Francis <alistair.francis@wdc.com> Reviewed-by: NChih-Min Chao <chihmin.chao@sifive.com> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
Current SiFive PRCI model only works with sifive_e machine, as it only emulates registers or PRCI block in the FE310 SoC. Rename the file name to make it clear that it is for sifive_e. This also prefix "sifive_e"/"SIFIVE_E" for all macros, variables and functions. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NChih-Min Chao <chihmin.chao@sifive.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
sifive_u machine does not use PRCI as of today. Remove the prci header inclusion. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
Like other binary files, the executable attribute of opensbi images should not be set. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
The inclusion of "target/riscv/cpu.h" is unnecessary in various sifive model drivers. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
Replace the call to hw_error() with qemu_log_mask(LOG_GUEST_ERROR,...) in various sifive models. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
There is no need to return fdt at the end of create_fdt() because it's already saved in s->fdt. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NChih-Min Chao <chihmin.chao@sifive.com> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
This removes "reg-names" and "riscv,max-priority" properties of the PLIC node from device tree. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NJonathan Behrens <fintelia@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
Some of the properties only have 1 cell so we should use qemu_fdt_setprop_cell() instead of qemu_fdt_setprop_cells(). Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
"linux,phandle" property is optional. Remove all instances in the sifive_u, virt and spike machine device trees. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
Commit a27bd6c7 ("Include hw/qdev-properties.h less") wrongly added "hw/hw.h" to sifive_prci.c and sifive_test.c. Another inclusion of "hw/hw.h" was later added via commit 650d103d ("Include hw/hw.h exactly where needed"), that resulted in duplicated inclusion of "hw/hw.h". Fixes: a27bd6c7 ("Include hw/qdev-properties.h less") Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
This adds a reset opcode for sifive_test device to trigger a system reset for testing purpose. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NPalmer Dabbelt <palmer@sifive.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
This adds 'info mem' command for RISC-V, to show virtual memory mappings that aids debugging. Rather than showing every valid PTE, the command compacts the output by merging all contiguous physical address mappings into one block and only shows the merged block mapping details. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NDr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: NPalmer Dabbelt <palmer@sifive.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
At present when "-bios image" is supplied, we just use the straight path without searching for the configured data directories. Like "-bios default", we add the same logic so that "-L" actually works. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
This adds a helper routine for finding firmware. It is currently used only for "-bios default" case. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Bin Meng 提交于
For RV32, the root page table's PPN has 22 bits hence its address bits could be larger than the maximum bits that target_ulong is able to represent. Use hwaddr instead. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Alistair Francis 提交于
Update the Hypervisor CSR addresses to match the v0.4 spec. Signed-off-by: NAlistair Francis <alistair.francis@wdc.com> Reviewed-by: NPalmer Dabbelt <palmer@sifive.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Alistair Francis 提交于
Let's create a function that tests if floating point support is enabled. We can then protect all floating point operations based on if they are enabled. This patch so far doesn't change anything, it's just preparing for the Hypervisor support for floating point operations. Signed-off-by: NAlistair Francis <alistair.francis@wdc.com> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: NChristophe de Dinechin <dinechin@redhat.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Alistair Francis 提交于
Signed-off-by: NAlistair Francis <alistair.francis@wdc.com> Reviewed-by: NJonathan Behrens <fintelia@gmail.com> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: NChih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Philippe Mathieu-Daudé 提交于
Use the always-compiled trace events, remove the now unused RISCV_DEBUG_PMP definition. Note pmpaddr_csr_read() could previously do out-of-bound accesses passing addr_index >= MAX_RISCV_PMPS. Signed-off-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Philippe Mathieu-Daudé 提交于
The RISC-V Physical Memory Protection is restricted to privileged modes. Restrict its compilation to QEMU system builds. Signed-off-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Guenter Roeck 提交于
The correct property name is clock-names, not clocks-names. Without this patch, the Ethernet driver fails to instantiate with the following error. macb 100900fc.ethernet: failed to get macb_clk (-2) macb: probe of 100900fc.ethernet failed with error -2 Signed-off-by: NGuenter Roeck <linux@roeck-us.net> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Guenter Roeck 提交于
The riscv uart needs valid clocks. This requires a refereence to the clock node. Since the SOC clock is not emulated by qemu, add a reference to a fixed clock instead. The clock-frequency entry in the uart node does not seem to be necessary, so drop it. In addition to a reference to the clock, the driver also needs an aliases entry for the serial node. Add it as well. Without this patch, the serial driver fails to instantiate with the following error message. sifive-serial 10013000.uart: unable to find controller clock sifive-serial: probe of 10013000.uart failed with error -2 when trying to boot Linux. Signed-off-by: NGuenter Roeck <linux@roeck-us.net> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Guenter Roeck 提交于
Add support for loading initrd with "-initrd <filename>" to the sifive_u machine. This lets us boot into Linux without disk drive. Signed-off-by: NGuenter Roeck <linux@roeck-us.net> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Peter Maydell 提交于
Switch the SPARC target from the old unassigned_access hook to the new do_transaction_failed hook. This will cause the "if transaction failed" code paths added in the previous commits to become active if the access is to an unassigned address. In particular we'll now handle bus errors during page table walks correctly (generating a translation error with the right kind of fault status). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Tested-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-id: 20190801183012.17564-8-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The dump_mmu() function does a ldl_phys() at the start, but then never uses the value it loads at all. Remove the unused code. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Tested-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-id: 20190801183012.17564-7-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Convert the mmu_probe() function to using address_space_ldl() rather than ldl_phys(), so we can explicitly detect memory transaction failures. This makes no practical difference at the moment, because ldl_phys() will return 0 on a transaction failure, and we treat transaction failures and 0 PDEs identically. However the spec says that MMU probe operations are supposed to update the fault status registers, and if we ever implement that we'll want to distinguish the difference. For the moment, just add a TODO comment about the bug. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Tested-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-id: 20190801183012.17564-6-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Currently we use the ldl_phys() function to read page table entries. With the unassigned_access hook in place, if these hit an unassigned area of memory then the hook will cause us to wrongly generate an exception with a fault address matching the address of the page table entry. Change to using address_space_ldl() so we can detect and correctly handle bus errors and give them their correct behaviour of causing a translation error with a suitable fault status register. Note that this won't actually take effect until we switch the over to using the do_translation_failed hook. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Tested-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-id: 20190801183012.17564-5-peter.maydell@linaro.org
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