1. 29 10月, 2015 6 次提交
  2. 28 10月, 2015 6 次提交
    • P
      Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging · 496feddd
      Peter Maydell 提交于
      target-i386: finally enable "check" mode by default
      
      # gpg: Signature made Wed 28 Oct 2015 14:13:10 GMT using RSA key ID 984DC5A6
      # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>"
      
      * remotes/ehabkost/tags/x86-pull-request:
        target-i386: Enable "check" mode by default
        target-i386: Don't left shift negative constant
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      496feddd
    • P
      Merge remote-tracking branch 'remotes/mcayland/tags/qemu-openbios-signed' into staging · 739680da
      Peter Maydell 提交于
      Update OpenBIOS images
      
      # gpg: Signature made Wed 28 Oct 2015 00:02:46 GMT using RSA key ID AE0F321F
      # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>"
      
      * remotes/mcayland/tags/qemu-openbios-signed:
        Update OpenBIOS images
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      739680da
    • M
      Update OpenBIOS images · 637016c2
      Mark Cave-Ayland 提交于
      Update OpenBIOS images to SVN r1353 built from submodule.
      Signed-off-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
      637016c2
    • E
      target-i386: Enable "check" mode by default · 15e41345
      Eduardo Habkost 提交于
      Current default behavior of QEMU is to silently disable features that
      are not supported by the host when a CPU model is requested in the
      command-line. This means that in addition to risking breaking guest ABI
      by default, we are silent about it.
      
      I would like to enable "enforce" by default, but this can easily break
      existing production systems because of the way libvirt makes assumptions
      about CPU models today (this will change in the future, once QEMU
      provide a proper interface for checking if a CPU model is runnable).
      
      But there's no reason we should be silent about it. So, change
      target-i386 to enable "check" mode by default so at least we have some
      warning printed to stderr (and hopefully logged somewhere) when QEMU
      disables a feature that is not supported by the host system.
      Reviewed-by: NIgor Mammedov <imammedo@redhat.com>
      Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
      15e41345
    • E
      target-i386: Don't left shift negative constant · 712b4243
      Eduardo Habkost 提交于
      Left shift of negative values is undefined behavior. Detected by clang:
        qemu/target-i386/translate.c:2423:26: runtime error:
          left shift of negative value -8
      
      This changes the code to reverse the sign after the left shift.
      Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
      712b4243
    • P
      Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20151027-1' into staging · c012e1b7
      Peter Maydell 提交于
      target-arm queue:
       * more EL2 preparation: handling for stage 2 translations
       * standardize debug macros in i.MX devices
       * improve error message in a corner case for virt board
       * disable live migration of KVM GIC if the kernel can't handle it
       * add SPSR_(ABT|UND|IRQ|FIQ) registers
       * handle non-executable page-straddling Thumb instructions
       * fix a "no 64-bit EL2" assumption in arm_excp_unmasked()
      
      # gpg: Signature made Tue 27 Oct 2015 16:03:31 GMT using RSA key ID 14360CDE
      # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
      # gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
      # gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
      
      * remotes/pmaydell/tags/pull-target-arm-20151027-1: (27 commits)
        target-arm: Add support for S1 + S2 MMU translations
        target-arm: Route S2 MMU faults to EL2
        target-arm: Add S2 translation to 32bit S1 PTWs
        target-arm: Add S2 translation to 64bit S1 PTWs
        target-arm: Add ARMMMUFaultInfo
        target-arm: Avoid inline for get_phys_addr
        target-arm: Add support for S2 page-table protection bits
        target-arm: Add computation of starting level for S2 PTW
        target-arm: lpae: Rename granule_sz to stride
        target-arm: lpae: Replace tsz with computed inputsize
        target-arm: Add support for AArch32 S2 negative t0sz
        target-arm: lpae: Move declaration of t0sz and t1sz
        target-arm: lpae: Make t0sz and t1sz signed integers
        target-arm: Add HPFAR_EL2
        i.MX: Standardize i.MX GPT debug
        i.MX: Standardize i.MX EPIT debug
        i.MX: Standardize i.MX FEC debug
        i.MX: Standardize i.MX CCM debug
        i.MX: Standardize i.MX AVIC debug
        i.MX: Standardize i.MX I2C debug
        ...
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      c012e1b7
  3. 27 10月, 2015 28 次提交