Current implementation of thumb mul instruction is implemented as a
32x32->64 multiply which then uses only 32 least significant bits of
the result. Replace that with a simple 32x32->32 multiply.
Signed-off-by: NJuha Riihimäki <juha.riihimaki@nokia.com>
Acked-by: NLaurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Revised patch for getting rid of tcg temporary variable leaks in
target-arm/translate.c. This version also includes the leak patch for
gen_set_cpsr macro, now converted as a static inline function, which I
sent earlier as a separate patch on top of this patch.
Signed-off-by: NJuha Riihimäki <juha.riihimaki@nokia.com>
Acked-by: NLaurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

lzcnt is a AMD Phenom/Barcelona added instruction returning the
number of leading zero bits in a word.
As this is similar to the "bsr" instruction, reuse the existing
code. There need to be some more changes, though, as lzcnt always
returns a valid value (in opposite to bsr, which has a special
case when the operand is 0).
lzcnt is guarded by the ABM CPUID bit (Fn8000_0001:ECX_5).
Signed-off-by: NAndre Przywara <andre.przywara@amd.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

(INT32_MIN / -1) triggers an overflow, and the result depends on the
host architecture (INT32_MIN on arm, -1 on ppc, SIGFPE on x86). Use a
test to output the correct value.
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
Acked-by: NLaurent Desnogues <laurent.desnogues@gmail.com>

Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
Acked-by: NLaurent Desnogues <laurent.desnogues@gmail.com>

Patchworks-ID: 35755
Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
Signed-off-by: NAmit Shah <amit.shah@redhat.com>
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>

The OPENED event gets sent also when qemu resets its state initially.
The consumers of the event aren't interested in receiving this event
on reset.

Patchworks-ID: 35288
Signed-off-by: NAmit Shah <amit.shah@redhat.com>
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>

The char event RESET is emitted when a char device is opened.
Give it a better name.

Patchworks-ID: 35287
Signed-off-by: NAmit Shah <amit.shah@redhat.com>
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>

At init, qemu_chr_reset is always called with initial_reset_issued set to 1.
So checking for it to be set is not necessary.

Patchworks-ID: 35286
Signed-off-by: NAmit Shah <amit.shah@redhat.com>
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>

Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

basic FreeBSD sysarch(2) handling
fixed syscall errno return
Signed-off-by: NJuergen Lock <nox@jelal.kn-bremen.de>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

No need to alias e300 core for each CPU package.
Differences between microcontrollers have to be implemented in a higher layer
than translate_init.c
Signed-off-by: NThomas Monjalon <thomas@monjalon.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add CPU declarations of MPC8343, MPC8343E, MPC8347 and MPC8347E.
Signed-off-by: NThomas Monjalon <thomas@monjalon.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Declare HID2 register.

Use high BATs for e300 (8 instead of 4).

Fix index of high BATs registers.
Before the fix, IBAT4-7 were overwriting IBAT0-3.
Signed-off-by: NFrançois Armand <francois.armand@os4i.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Use load_reg_var() instead of accessing cpu_R[rn] directly to generate
correct code when rn = 15.
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Use load_reg_var() instead of accessing cpu_R[rn] directly to generate
correct code when rn = 15.
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: NFilip Navara <filip.navara@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: NFilip Navara <filip.navara@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: NFilip Navara <filip.navara@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: NFilip Navara <filip.navara@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: NFilip Navara <filip.navara@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: NFilip Navara <filip.navara@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: NFilip Navara <filip.navara@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

The goal is eventually to get rid of all cpu_T register usage and to use
just short-lived tmp/tmp2 registers. This patch converts all the places where
cpu_T was used in the Thumb code and replaces it with explicit TCG register
allocation.
Signed-off-by: NFilip Navara <filip.navara@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Uninitialized register was used instead of proper TCG variable.
Signed-off-by: NFilip Navara <filip.navara@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

The neon_trn_u8, neon_trn_u16, neon_unzip_u8, neon_zip_u8 and neon_zip_u16
helpers used fixed registers to return values. This patch replaces that with
TCG code, so T0/T1 is no longer directly used by the helper functions.

Bugs in the gen_neon_unzip register load code were also fixed.
Signed-off-by: NFilip Navara <filip.navara@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: NFilip Navara <filip.navara@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: NFilip Navara <filip.navara@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

The encoding of 'IA' and 'DB' conditions was swapped.
SRS instruction must store banked SPSR instead of CPSR at the specific address.
Missing 'return' statement at the end of RFE handling.
Fixed write-back code to reference correct registers.

From: Hyeonsung Jang <hsjang@ok-labs.com>
Signed-off-by: NFilip Navara <filip.navara@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: NFilip Navara <filip.navara@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: NFilip Navara <filip.navara@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

The temporary variable cache in no longer need since tcg_temp_free was introduced.
Signed-off-by: NFilip Navara <filip.navara@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Currently each read/write of ARM register involves a LD/ST TCG operation. This
patch uses TCG memory-backed registers to represent the ARM register set. With
memory-backed registers the LD/ST operations are transparently generated by TCG
and host registers could be used to optimize the generated code.
Signed-off-by: NFilip Navara <filip.navara@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

This patch fixes the mount call. GUEST_BASE shouldn't be added to a NULL pointer on arg5 . failing call:
mount("rootfs", "/", 0x47a78, MS_MGC_VAL|MS_REMOUNT, 0x10000) = -1 EFAULT (Bad address)

correct call:
mount("rootfs", "/", 0x37ab0, MS_MGC_VAL|MS_REMOUNT, NULL) = 0

Signed-off-by:  Jan-Simon Möller  <dl9pf@gmx.de>
Signed-off-by: NRiku Voipio <riku.voipio@iki.fi>

Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>