- 11 11月, 2008 18 次提交
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由 aurel32 提交于
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5687 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5686 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5685 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Optimize code generation in gen_compute_branch1(): - Directly use I32 variables instead of converting values from _tl to _i32 and back to _tl. - Write the result directly to bcond instead of passing by a local variable. - Temp variables are valid up to and *including* the brcond instruction. Use them instead of temp local variables. Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5684 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Optimize code generation in gen_movc*(): - Temp variables are valid up to and *including* the brcond instruction. Use them instead of temp local variables. - Avoid using temporary variables to transfer values. - Access fpu_fcr31 directly in gen_movcf_ps(). Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5683 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Optimize code generation in gen_farith(): - Temp variables are valid up to and *including* the brcond instruction. Use them instead of temp local variables. Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5682 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Optimize code generation in gen_muldiv(): - Don't do sign extension when the value is already guaranteed to be sign extended (otherwise, results are marked as UNPREDICTABLE). - Access the LO, HI registers directly instead of writting them through a temporary variable. Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5681 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Optimize code generation in gen_arith()/gen_arith_imm(): - Don't do sign extension when the value is already guaranteed to be sign extended (otherwise, results are marked as UNPREDICTABLE). - When the value is sign extended, compare the value to 0 instead of testing bit 31/63. - Temp variables are valid up to and *including* the brcond instruction. Use them instead of temp local variables. Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5680 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Bit shuffle operations can be written with very few TCG instructions (between 5 and 8), so it is worth converting them to TCG. This code also move all bit shuffle generation code to a separate function in order to have a cleaner exception code path, that is it doesn't store back the TCG register to the target register after the exception, as the TCG register doesn't exist anymore. Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5679 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Bitfield operations can be written with very few TCG instructions (between 2 and 5), so it is worth converting them to TCG. Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5678 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Instead of dynamically generating different code depending on the UX flag, add a new flag in ctx->flags to generate different code. Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5677 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
The user mode can be tested at translation time using ctx->hflags. This simplifies gen_op_addr_add(). Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5676 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
We obviously don't need to use a temporary variable to write PC. Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5675 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
This patch attempts to fix mft* helpers and the associated TCG calls. mft* helpers do not take a register in argument, however: - some helpers are called with an argument while they do not take one. - some helpers are declared with an argument they don't use. Acked-by: NThiemo Seufer <ths@networkno.de> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5674 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Move tcg_temp_free() out of the conditional part to make sure the TCG temporary variable is freed in all cases. Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> Acked-by: NThiemo Seufer <ths@networkno.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5673 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
On Alpha the target to native fcntl definitions were missing. Because of this, programs trying to open files with the O_CREAT option were getting O_APPEND instead, etc. This was keeping gcc from the spec benchmarks from running, among other things. (Vince Weaver) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5672 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Noticed by Chris Krumme. Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5671 c046a42c-6fe2-441c-8c8c-71466251a162
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由 malc 提交于
LD/STD/LWA require displacement to be multiple of 4, provide tcg_out_ldsta which checks the supplied displacement and falls back on indexed variant when the check fails. All uses of LD/STD/LWA outside of tcg_out_ldst appear to be safe. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5670 c046a42c-6fe2-441c-8c8c-71466251a162
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- 10 11月, 2008 14 次提交
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由 aliguori 提交于
We don't need to use cpu_loop_exit() because we never use the condition codes so everything can be folded into a single case. Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5669 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5668 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
The cmpbge instruction should compare all 8 bytes of one 64-bit value with another. However, we were looping with a < 7 condition which was skipping the top byte. So if we were doing a compare where the top byte was important, we could get the wrong result (this notably breaks the strlen() function with certain sized strings). (Vince Weaver) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5667 c046a42c-6fe2-441c-8c8c-71466251a162
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由 balrog 提交于
env->*dt.base should fit target address space, so we should use target_mmap to allocate them. Signed-off-by: NKirill A. Shutemov <kirill@shutemov.name> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5666 c046a42c-6fe2-441c-8c8c-71466251a162
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由 balrog 提交于
result in a cryptic error (and an abort): qemu: block-vvfat.c:97: array_get: Assertion `index < array->next' failed. Aborted Turn this into an actually useful error message: Directory does not fit in FAT16 (capacity 504MB) qemu: could not open disk image fat:$DIR/ git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5665 c046a42c-6fe2-441c-8c8c-71466251a162
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由 balrog 提交于
x86 CPUs feature extended family/model bits in CPUID leaf 0000_0001|EAX. Refer to page 10 in: http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25481.pdf Those bits are necessary to model newer AMD CPUs: -cpu qemu64,family=15,model=65,stepping=3 or -cpu qemu64,family=16,model=4,stepping=2 Signed-off-by: NAndre Przywara <andre.przywara@amd.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5664 c046a42c-6fe2-441c-8c8c-71466251a162
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由 blueswir1 提交于
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5663 c046a42c-6fe2-441c-8c8c-71466251a162
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由 blueswir1 提交于
Also fix which argument gets negated in fandnot[12] and fornot[12] git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5662 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5661 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5660 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
- Rename to gen_op_arith_neg for consistency with other functions. - Correctly free TCG temp variable. - Fix the return value in 64-bit mode in case of overflow. Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5659 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
gen_op_arith_divw(): - "deoptimize" gen_op_arith_divw to make it more readable. - Correctly free TCG temp variable gen_op_arith_divd(): - Call the right function. Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5658 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5657 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5656 c046a42c-6fe2-441c-8c8c-71466251a162
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- 09 11月, 2008 6 次提交
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由 blueswir1 提交于
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5655 c046a42c-6fe2-441c-8c8c-71466251a162
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由 balrog 提交于
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5654 c046a42c-6fe2-441c-8c8c-71466251a162
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由 balrog 提交于
Also optimise qemu_strdup by using memcpy - using pstrcpy is usually suboptimal. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5653 c046a42c-6fe2-441c-8c8c-71466251a162
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由 balrog 提交于
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5652 c046a42c-6fe2-441c-8c8c-71466251a162
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由 balrog 提交于
The use of strncat and strndup was correct, pstrcpy and pstrdup wasn't. I'll try to restore building on non-gnu OSes in a later commit. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5651 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aliguori 提交于
Generate an option rom instead of using a hijacked boot sector for kernel booting. This just requires adding a small option ROM header and a few more instructions to the boot sector to take over the int19 vector and run our boot code. A disk is no longer needed when using -kernel on x86. Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5650 c046a42c-6fe2-441c-8c8c-71466251a162
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- 08 11月, 2008 2 次提交
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由 aurel32 提交于
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5649 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
It looks like the i386 runs out of registers for allocation due to too many global registers allocated by the ppc target. Here is a quick and dirty fix that seems to solve the problem. This should be considered as temporary. Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5648 c046a42c-6fe2-441c-8c8c-71466251a162
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