Most targets did not name the enum; tci used TCGRegister.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Reviewed-by: NAndreas Färber <afaerber@suse.de>
Reviewed-by: NStefan Weil <sw@weilnetz.de>
Signed-off-by: NAlexander Graf <agraf@suse.de>

Removing the only tabs in the file.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: Nmalc <av1474@comtv.ru>

The error being caused by the failure to copy the other half of
the input to the output after having narrowed the deposit operation.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: Nmalc <av1474@comtv.ru>

Unlike other tcg target code generators, this one does not generate
machine code for some cpu. It generates machine independent bytecode
which is interpreted later.

This allows running QEMU on any host.

Interpreted bytecode is slower than direct execution of generated
machine code.
Signed-off-by: NStefan Weil <sw@weilnetz.de>

tcg_op_defs was already a global array.

The tci disassembler also needs ARRAY_SIZE(tcg_op_defs),
so add a new global constant with this value.
Signed-off-by: NStefan Weil <sw@weilnetz.de>

Targets may use a non standard definition of tcg_tb_exec
by defining this macro in their tcg_target.h.

This is used here by ppc. It will be used by the TCG interpreter, too.

Cc: malc <av1474@comtv.ru>
Signed-off-by: NStefan Weil <sw@weilnetz.de>

If the deposit replaces the entire word, optimize to a move.

If we're inserting to the top of the word, avoid the mask of arg2
as we'll be shifting out all of the garbage and shifting in zeros.

If the host is 32-bit, reduce a 64-bit deposit to a 32-bit deposit
when possible.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Signed-off-by: NStefan Weil <sw@weilnetz.de>
Signed-off-by: NStefan Hajnoczi <stefanha@linux.vnet.ibm.com>

Remove the unused function tcg_out_addi() from the s390 TCG backend;
this brings it into line with other backends.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Acked-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Remove the unused function tcg_out_addi() from the ia64 TCG backend;
this brings it into line with other backends.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

x86 cannot provide an optimized generic deposit implementation. But at
least for a few special cases, namely for writing bits 0..7, 8..15, and
0..15, versions using only a single instruction are feasible.
Introducing such limited support improves emulating 16-bit x86 code on
x86, but also rarer cases where 32-bit or 64-bit code accesses bytes or
words.
Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Remove the unused function tcg_out_addi() from the ARM TCG backend;
this fixes a compilation failure on ARM hosts with newer gcc.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Signed-off-by: NStefan Weil <weil@mail.berlios.de>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

These functions are defined in the tcg target specific file
tcg-target.c.

The forward declarations assert that every tcg target uses
the same function prototype.
Signed-off-by: NStefan Weil <weil@mail.berlios.de>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

It is now declared for all tcg targets in tcg.h,
so the tcg target specific declarations are redundant.
Signed-off-by: NStefan Weil <weil@mail.berlios.de>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

TCG_TARGET_REG_BITS can be determined by the compiler,
so there is no need to declare it for each individual tcg target.

This is especially important for new tcg targets
which will be supported by the tcg interpreter.
Signed-off-by: NStefan Weil <weil@mail.berlios.de>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

The second register is only needed for 32 bit hosts.

Cc: Vassili Karpov <av1474@comtv.ru>
Fine-with-me'd-by: Vassili Karpov <av1474@comtv.ru>
Signed-off-by: NStefan Weil <weil@mail.berlios.de>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

The second register is only needed for 32 bit hosts.

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: NStefan Weil <weil@mail.berlios.de>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

The second register is only needed for 32 bit hosts.

Cc: Alexander Graf <agraf@suse.de>
Acked-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NStefan Weil <weil@mail.berlios.de>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

The second register is never used for ia64 hosts.

Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NStefan Weil <weil@mail.berlios.de>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

The second register is only needed for 32 bit hosts.
Signed-off-by: NStefan Weil <weil@mail.berlios.de>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

The ppc64 code generation backend uses an rldicr (Rotate Left Double
Immediate and Clear Right) instruction to implement zero extension of
a 32 bit quantity to a 64 bit quantity (INDEX_op_ext32u_i64).  However
this is wrong - this instruction clears specified low bits of the
value, instead of high bits as we require for a zero extension.  It
should instead use an rldicl (Rotate Left Double Immediate and Clear
Left) instruction.

Presumably amongst other things, this causes the SLOF firmware image
used with -M pseries to not boot on a ppc64 host.

It appears this bug was exposed by commit
0bf1dbdc (tcg/ppc64: fix 16/32 mixup)
which enabled the use of the op_ext32u_i64 operation on the ppc64
backend.
Signed-off-by: NThomas Huth <thuth@de.ibm.com>
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Nmalc <av1474@comtv.ru>

Move the declaration and initialisation of some variables in
tcg_out_qemu_ld and tcg_out_qemu_st inside CONFIG_SOFTMMU, to
avoid the "variable set but not used" warning of gcc 4.6.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: Nmalc <av1474@comtv.ru>

Use enum TCGOpcode instead of plain old int so that the name of
current op can be seen in GDB. Add a default case to switch
so that GCC does not complain about unhandled enum cases.
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Signed-off-by: NRichard Henderson <rth@twiddle.net>
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com>

Signed-off-by: Nmalc <av1474@comtv.ru>

Signed-off-by: Nmalc <av1474@comtv.ru>

Signed-off-by: Nmalc <av1474@comtv.ru>

Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

By always defining these symbols, we can eliminate a lot of ifdefs.

To allow this to be checked reliably, the semantics of the
TCG_TARGET_HAS_* macros must be changed from def/undef to true/false.
This allows even more ifdefs to be removed, converting them into
C if statements.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

This allows the simplification of the op_bits function from
tcg/optimize.c.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

qemu_malloc/qemu_free no longer exist after this commit.
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>

Copy propagation introduced in 22613af4
considered only global registers. However, register temps and stack
allocated locals must be handled differently because register temps
don't survive across brcond.

Fix by propagating only within same class of temps.
Tested-by: NStefan Weil <weil@mail.berlios.de>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Fix incorrect logic and typos in previous commit
1bfd07bd.
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Fix breakage by a640f031
and 55c0975c.

Some TCG targets don't implement all TCG ops, so make
optimizing those conditional.
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Perform constant folding for NOT and EXT{8,16,32}{S,U} operations.
Signed-off-by: NKirill Batuzov <batuzovk@ispras.ru>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Perform constant forlding for SHR, SHL, SAR, ROTR, ROTL operations.
Signed-off-by: NKirill Batuzov <batuzovk@ispras.ru>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Perform constant folding for AND, OR, XOR operations.
Signed-off-by: NKirill Batuzov <batuzovk@ispras.ru>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>