1. 01 3月, 2017 28 次提交
  2. 28 2月, 2017 12 次提交
    • P
      Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170228' into staging · 1bbe5dc6
      Peter Maydell 提交于
      target-arm queue:
       * raspi2: implement RNG module
       * raspi2: implement new SD card controller (but don't wire it up)
       * sdhci: bugfixes for block transfers
       * virt: fix cpu object reference leak
       * Add missing fp_access_check() to aarch64 crypto instructions
       * cputlb: Don't assume do_unassigned_access() never returns
       * virt: Add a user option to disallow ITS instantiation
       * i.MX timers: fix reset handling
       * ARMv7M NVIC: rewrite to fix broken priority handling and masking
       * exynos: Fix proper mapping of CPUs by providing real cluster ID
       * exynos: Fix Linux kernel division by zero for PLLs
      
      # gpg: Signature made Tue 28 Feb 2017 12:40:51 GMT
      # gpg:                using RSA key 0x3C2525ED14360CDE
      # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
      # gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
      # gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
      # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE
      
      * remotes/pmaydell/tags/pull-target-arm-20170228: (27 commits)
        hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID
        hw/arm/exynos: Fix Linux kernel division by zero for PLLs
        bcm2835_sdhost: add bcm2835 sdhost controller
        armv7m: Allow SHCSR writes to change pending and active bits
        armv7m: Raise correct kind of UsageFault for attempts to execute ARM code
        armv7m: Check exception return consistency
        armv7m: Extract "exception taken" code into functions
        armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE
        armv7m: Simpler and faster exception start
        armv7m: Remove unused armv7m_nvic_acknowledge_irq() return value
        armv7m: Escalate exceptions to HardFault if necessary
        arm: gic: Remove references to NVIC
        armv7m: Fix condition check for taking exceptions
        armv7m: Rewrite NVIC to not use any GIC code
        armv7m: Implement reading and writing of PRIGROUP
        armv7m: Rename nvic_state to NVICState
        ARM i.MX timers: fix reset handling
        hw/arm/virt: Add a user option to disallow ITS instantiation
        cputlb: Don't assume do_unassigned_access() never returns
        Add missing fp_access_check() to aarch64 crypto instructions
        ...
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      1bbe5dc6
    • P
      Merge remote-tracking branch 'remotes/cody/tags/block-pull-request' into staging · c8c0a1a7
      Peter Maydell 提交于
      # gpg: Signature made Tue 28 Feb 2017 04:34:34 GMT
      # gpg:                using RSA key 0xBDBE7B27C0DE3057
      # gpg: Good signature from "Jeffrey Cody <jcody@redhat.com>"
      # gpg:                 aka "Jeffrey Cody <jeff@codyprime.org>"
      # gpg:                 aka "Jeffrey Cody <codyprime@gmail.com>"
      # Primary key fingerprint: 9957 4B4D 3474 90E7 9D98  D624 BDBE 7B27 C0DE 3057
      
      * remotes/cody/tags/block-pull-request:
        iscsi: add missing colons to the qapi docs
        block/mirror: fix broken sparseness detection
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      c8c0a1a7
    • P
      Merge remote-tracking branch 'remotes/rth/tags/pull-axp-20170228' into staging · a57aaa4e
      Peter Maydell 提交于
      Enable MTTCG for Alpha guest
      
      # gpg: Signature made Tue 28 Feb 2017 00:43:17 GMT
      # gpg:                using RSA key 0xAD1270CC4DD0279B
      # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
      # gpg:                 aka "Richard Henderson <rth@redhat.com>"
      # gpg:                 aka "Richard Henderson <rth@twiddle.net>"
      # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC  16A4 AD12 70CC 4DD0 279B
      
      * remotes/rth/tags/pull-axp-20170228:
        target/alpha: Enable MTTCG by default
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      a57aaa4e
    • K
      hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID · f3a6339a
      Krzysztof Kozlowski 提交于
      The Exynos4210 has cluster ID 0x9 in its MPIDR register (raw value
      0x8000090x).  If this cluster ID is not provided, then Linux kernel
      cannot map DeviceTree nodes to MPIDR values resulting in kernel
      warning and lack of any secondary CPUs:
      
          DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map
          ...
          smp: Bringing up secondary CPUs ...
          smp: Brought up 1 node, 1 CPU
          SMP: Total of 1 processors activated (24.00 BogoMIPS).
      
      Provide a cluster ID so Linux will see proper MPIDR and will try to
      bring the secondary CPU online.
      Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
      Message-id: 20170226200142.31169-2-krzk@kernel.org
      Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      f3a6339a
    • K
      hw/arm/exynos: Fix Linux kernel division by zero for PLLs · 1e0228fd
      Krzysztof Kozlowski 提交于
      Without any clock controller, the Linux kernel was hitting division by
      zero during boot or with clk_summary:
      [    0.000000] [<c031054c>] (unwind_backtrace) from [<c030ba6c>] (show_stack+0x10/0x14)
      [    0.000000] [<c030ba6c>] (show_stack) from [<c05b2660>] (dump_stack+0x88/0x9c)
      [    0.000000] [<c05b2660>] (dump_stack) from [<c05b11a4>] (Ldiv0+0x8/0x10)
      [    0.000000] [<c05b11a4>] (Ldiv0) from [<c06ad1e0>] (samsung_pll45xx_recalc_rate+0x58/0x74)
      [    0.000000] [<c06ad1e0>] (samsung_pll45xx_recalc_rate) from [<c0692ec0>] (clk_register+0x39c/0x63c)
      [    0.000000] [<c0692ec0>] (clk_register) from [<c125d360>] (samsung_clk_register_pll+0x2e0/0x3d4)
      [    0.000000] [<c125d360>] (samsung_clk_register_pll) from [<c125d7e8>] (exynos4_clk_init+0x1b0/0x5e4)
      [    0.000000] [<c125d7e8>] (exynos4_clk_init) from [<c12335f4>] (of_clk_init+0x17c/0x210)
      [    0.000000] [<c12335f4>] (of_clk_init) from [<c1204700>] (time_init+0x24/0x2c)
      [    0.000000] [<c1204700>] (time_init) from [<c1200b2c>] (start_kernel+0x24c/0x38c)
      [    0.000000] [<c1200b2c>] (start_kernel) from [<4020807c>] (0x4020807c)
      
      Provide stub for clock controller returning reset values for PLLs.
      Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
      Message-id: 20170226200142.31169-1-krzk@kernel.org
      Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      1e0228fd
    • C
      bcm2835_sdhost: add bcm2835 sdhost controller · 43ddc182
      Clement Deschamps 提交于
      This adds the BCM2835 SDHost controller from Arasan.
      Signed-off-by: NClement Deschamps <clement.deschamps@antfield.fr>
      Message-id: 20170224164021.9066-2-clement.deschamps@antfield.fr
      Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      43ddc182
    • P
      armv7m: Allow SHCSR writes to change pending and active bits · 5db53e35
      Peter Maydell 提交于
      Implement the NVIC SHCSR write behaviour which allows pending and
      active status of some exceptions to be changed.
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
      5db53e35
    • P
      armv7m: Raise correct kind of UsageFault for attempts to execute ARM code · e13886e3
      Peter Maydell 提交于
      M profile doesn't implement ARM, and the architecturally required
      behaviour for attempts to execute with the Thumb bit clear is to
      generate a UsageFault with the CFSR INVSTATE bit set.  We were
      incorrectly implementing this as generating an UNDEFINSTR UsageFault;
      fix this.
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
      e13886e3
    • P
      armv7m: Check exception return consistency · aa488fe3
      Peter Maydell 提交于
      Implement the exception return consistency checks
      described in the v7M pseudocode ExceptionReturn().
      
      Inspired by a patch from Michael Davidsaver's series, but
      this is a reimplementation from scratch based on the
      ARM ARM pseudocode.
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
      aa488fe3
    • P
      armv7m: Extract "exception taken" code into functions · 39ae2474
      Peter Maydell 提交于
      Extract the code from the tail end of arm_v7m_do_interrupt() which
      enters the exception handler into a pair of utility functions
      v7m_exception_taken() and v7m_push_stack(), which correspond roughly
      to the pseudocode PushStack() and ExceptionTaken().
      
      This also requires us to move the arm_v7m_load_vector() utility
      routine up so we can call it.
      
      Handling illegal exception returns has some cases where we want to
      take a UsageFault either on an existing stack frame or with a new
      stack frame but with a specific LR value, so we want to be able to
      call these without having to go via arm_v7m_cpu_do_interrupt().
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
      39ae2474
    • M
      armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE · 14790f73
      Michael Davidsaver 提交于
      The VECTCLRACTIVE and VECTRESET bits in the AIRCR are both
      documented as UNPREDICTABLE if you write a 1 to them when
      the processor is not halted in Debug state (ie stopped
      and under the control of an external JTAG debugger).
      Since we don't implement Debug state or emulated JTAG
      these bits are always UNPREDICTABLE for us. Instead of
      logging them as unimplemented we can simply log writes
      as guest errors and ignore them.
      Signed-off-by: NMichael Davidsaver <mdavidsaver@gmail.com>
      [PMM: change extracted from another patch; commit message
       constructed from scratch]
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
      Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
      14790f73
    • M
      armv7m: Simpler and faster exception start · a25dc805
      Michael Davidsaver 提交于
      All the places in armv7m_cpu_do_interrupt() which pend an
      exception in the NVIC are doing so for synchronous
      exceptions. We know that we will always take some
      exception in this case, so we can just acknowledge it
      immediately, rather than returning and then immediately
      being called again because the NVIC has raised its outbound
      IRQ line.
      Signed-off-by: NMichael Davidsaver <mdavidsaver@gmail.com>
      [PMM: tweaked commit message; added DEBUG to the set of
      exceptions we handle immediately, since it is synchronous
      when it results from the BKPT instruction]
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
      a25dc805