- 16 8月, 2012 1 次提交
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由 Anthony Liguori 提交于
mingw32 seems to want the declaration to also carry the weak attribute. Strangely, gcc on Linux absolutely does not want the declaration to be marked as weak. This may not be the right fix, but it seems to do the trick. Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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- 14 8月, 2012 1 次提交
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由 Anthony Liguori 提交于
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com> Signed-off-by: NLuiz Capitulino <lcapitulino@redhat.com>
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- 25 6月, 2012 1 次提交
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由 Stefan Weil 提交于
This fixes a compiler error when QEMU was configured with --enable-debug. Signed-off-by: NStefan Weil <sw@weilnetz.de> Signed-off-by: NAlexander Graf <agraf@suse.de>
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- 24 6月, 2012 8 次提交
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由 Alexander Graf 提交于
The MAS registers on BookE are all 32 bit wide, except for MAS2, which can hold up to 64 bit on 64 bit capable CPUs. Reflect this in the SPR setting code, so that the guest can never write invalid values in them. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
This patch moves the debug #ifdef'ed SPR trace generation into its own function, so we can call it from multiple places. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
This patch adds e5500's CPU initialization to the TCG CPU initialization code. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
IVPR can either hold 32 or 64 bit addresses, depending on the CPU type. Let the CPU initialization function pass in its mask itself, so we can easily extend it. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Benjamin Herrenschmidt 提交于
More recent Power server chips (i.e. based on the 64 bit hash MMU) support more than just the traditional 4k and 16M page sizes. This can get quite complicated, because which page sizes are supported, which combinations are supported within an MMU segment and how these page sizes are encoded both in the SLB entry and the hash PTE can vary depending on the CPU model (they are not specified by the architecture). In addition the firmware or hypervisor may not permit use of certain page sizes, for various reasons. Whether various page sizes are supported on KVM, for example, depends on whether the PR or HV variant of KVM is in use, and on the page size of the memory backing the guest's RAM. This patch adds information to the CPUState and cpu defs to describe the supported page sizes and encodings. Since TCG does not yet support any extended page sizes, we just set this to NULL in the static CPU definitions, expanding this to the default 4k and 16M page sizes when we initialize the cpu state. When using KVM, however, we instead determine available page sizes using the new KVM_PPC_GET_SMMU_INFO call. For old kernels without that call, we use some defaults, with some guesswork which should do the right thing for existing HV and PR implementations. The fallback might not be correct for future versions, but that's ok, because they'll have KVM_PPC_GET_SMMU_INFO. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Blue Swirl 提交于
Add an explicit CPUPPCState parameter instead of relying on AREG0. Signed-off-by: NBlue Swirl <blauwirbel@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Blue Swirl 提交于
Add an explicit CPUPPCState parameter instead of relying on AREG0. Signed-off-by: NBlue Swirl <blauwirbel@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Blue Swirl 提交于
Add an explicit CPUPPCState parameter instead of relying on AREG0. Signed-off-by: NBlue Swirl <blauwirbel@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NAlexander Graf <agraf@suse.de>
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- 02 5月, 2012 1 次提交
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由 Alexander Graf 提交于
When initializing the e500 code, we need to expose its cache line size for user and system mode, while the mmu details are only interesting for system emulation. Split the 2 switch statements apart, allowing us to #ifdef out the mmu parts for user mode emulation while keeping all cache information consistent. Signed-off-by: NAlexander Graf <agraf@suse.de>
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- 16 4月, 2012 1 次提交
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由 Meador Inge 提交于
commit f7aa5583 pulled the dcache and icache line size initialization inside of a '#if !defined(CONFIG_USER_ONLY)' block. This is not correct because instructions like 'dcbz' need the dcache size initialized even for user mode. Signed-off-by: NMeador Inge <meadori@codesourcery.com> Cc: Varun Sethi <Varun.Sethi@freescale.com> [AF: Simplify #ifdefs by using cache line size 32 for *-user as before] Suggested-by: NScott Wood <scottwood@freescale.com> Signed-off-by: NAndreas Färber <afaerber@suse.de>
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- 15 4月, 2012 5 次提交
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由 Stefan Weil 提交于
This changes nothing for other hosts. Signed-off-by: NStefan Weil <sw@weilnetz.de> Signed-off-by: NAndreas Färber <afaerber@suse.de>
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由 Andreas Färber 提交于
Move code from cpu_state_reset() into ppc_cpu_reset(). Reorder #include of helper_regs.h to use it in translate_init.c. Adjust whitespace and add braces. Signed-off-by: NAndreas Färber <afaerber@suse.de> Acked-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Andreas Färber 提交于
Move code not dependent on ppc_def_t from cpu_ppc_init() into an initfn. Signed-off-by: NAndreas Färber <afaerber@suse.de> Acked-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Andreas Färber 提交于
Embed CPUPPCState as first member of PowerPCCPU. Distinguish between "powerpc-cpu", "powerpc64-cpu" and "embedded-powerpc-cpu". Let CPUClass::reset() call cpu_state_reset() for now. Signed-off-by: NAndreas Färber <afaerber@suse.de> Acked-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 David Gibson 提交于
On target-ppc, our table of CPU types and features encodes the features as found on the hardware, regardless of whether these features are actually usable under TCG or KVM. We already have cases where the information from the cpu table must be fixed up to account for limitations in the emulation method we're using. e.g. TCG does not support the DFP and VSX instructions and KVM needs different numbering of the CPUs in order to tell it the correct thread to core mappings. This patch cleans up these hacks to handle emulation limitations by consolidating them into a pair of functions specifically for the purpose. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> [AF: Style and typo fixes, rename new functions and drop ppc_def_t arg] Signed-off-by: NAndreas Färber <afaerber@suse.de>
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- 07 4月, 2012 1 次提交
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由 Stefan Weil 提交于
The official spelling is QEMU. Signed-off-by: NStefan Weil <sw@weilnetz.de> Reviewed-by: NAndreas Färber <afaerber@suse.de> [blauwirbel@gmail.com: fixed comment style in hw/sun4m.c] Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 15 3月, 2012 4 次提交
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由 Meador Inge 提交于
'POWERPC_INSNS2_DEFAULT' was defined incorrectly which was causing the opcode table creation code to erroneously register 'eieio' and 'mbar' for the "default" processor: ** ERROR: opcode 1a already assigned in opcode table 16 *** ERROR: unable to insert opcode [1f-16-1a] *** ERROR initializing PowerPC instruction 0x1f 0x16 0x1a Signed-off-by: NMeador Inge <meadori@codesourcery.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Nathan Whitehorn 提交于
The POWER7 emulation is missing the Processor Identification Register, mandatory in recent POWER CPUs, that is required for SMP on at least some operating systems (e.g. FreeBSD) to function properly. This patch copies the existing PIR code from the other CPUs that implement it. Signed-off-by: NNathan Whitehorn <nwhitehorn@freebsd.org> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Thomas Huth 提交于
These instructions for loading and storing byte-swapped 64-bit values have been introduced in PowerISA 2.06. Signed-off-by: NThomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Andreas Färber 提交于
Scripted conversion: sed -i "s/CPUState/CPUPPCState/g" target-ppc/*.[hc] sed -i "s/#define CPUPPCState/#define CPUState/" target-ppc/cpu.h Signed-off-by: NAndreas Färber <afaerber@suse.de> Acked-by: NAnthony Liguori <aliguori@us.ibm.com>
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- 02 2月, 2012 5 次提交
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由 Alexander Graf 提交于
When running Linux on e500 with powersave-nap enabled, Linux tries to read out the L1CFG0 register and calculates some things from it. Passing 0 there ends up in a division by 0, resulting in -1, resulting in badness. So let's populate the L1CFG0 register with reasonable defaults. That way guests aren't completely confused. Reported-by: NShrijeet Mukherjee <shm@cumulusnetworks.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
The e500mc implements Embedded.Processor Control, so enable it and thus enable guests to IPI each other. This makes -smp work with -cpu e500mc. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
The e500 CPUs don't use 440's msync which falls on the same opcode IDs, but instead use the real powerpc sync instruction. This is important, since the invalid mask differs between the two. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
E500mc supports IVORs 36-41. Add them to the support mask. Drop SPE support too. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
Our code only knows IVORs up to 37. Add the new ones defined in ISA 2.06 from 38 - 42. Signed-off-by: NAlexander Graf <agraf@suse.de> Reviewed-by: NAndreas Färber <afaerber@suse.de>
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- 21 1月, 2012 1 次提交
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由 Alexander Graf 提交于
Now that we have 440 TLB emulation, we can also support running the 440EP CPU target in system emulation mode. Signed-off-by: NAlexander Graf <agraf@suse.de>
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- 03 1月, 2012 1 次提交
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由 Varun Sethi 提交于
This core is found on chips such as p4080, p3041, p2040, and p5020. More needs to be done to make this viable for TCG (such as missing SPRs and instructions), but this suffices to get KVM running with appropriate kernel support. Signed-off-by: NVarun Sethi <Varun.Sethi@freescale.com> [scottwood@freescale.com: tweak some flags] Signed-off-by: NScott Wood <scottwood@freescale.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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- 31 10月, 2011 6 次提交
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由 David Gibson 提交于
The CPU state contains two bitmaps, initialized from the CPU spec which describes which instructions are implemented on the CPU. A couple of bits are defined which cover instructions (VSX and DFP) which are not currently implemented in TCG. So far, these are only used to handle the case of -cpu host because a KVM guest can use the instructions when the host CPU supports them. However, it's a mild layering violation to simply not include those bits in the CPU descriptions for those CPUs that do support them, just because we can't handle them in TCG. This patch corrects the situation, so that the instruction bits _are_ shown correctly in the cpu spec table, but are masked out from the cpu state in the non-KVM case. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 David Gibson 提交于
Currently, when KVM is enabled, the pseries machine checks if the host CPU supports VMX, VSX and/or DFP instructions and advertises accordingly in the guest device tree. It does this regardless of what CPU is selected on the command line. On the other hand, when in TCG mode, it never advertises any of these facilities, even basic VMX (Altivec) which is supported in TCG. Now that we have a -cpu host option for ppc, it is fairly straightforward to fix both problems. This patch changes the -cpu host code to override the basic cpu spec derived from the PVR with information queried from the host avout VMX, VSX and DFP capability. The pseries code then uses the instruction availability advertised in the cpu state to set the guest device tree correctly for both the KVM and TCG cases. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
The sole reason we have the ppcemb target is to support MMUs that have less than the usual 4k possible page size. There are very few of these chips and I don't want to add additional QA and testing burden to everyone to ensure that code still works when TARGET_PAGE_SIZE is not 4k. So this patch disables all CPUs except for MMU_BOOKE capable ones from the ppcemb target. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 David Gibson 提交于
This patch adds cpu specs to the table for POWER7 revisions 2.1 and 2.3. This allows -cpu host to be used on these host cpus. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 David Gibson 提交于
For convenience with kvm, x86 allows the user to specify -cpu host on the qemu command line, which means make the guest cpu the same as the host cpu. This patch implements the same option for ppc targets. For now, this just read the host PVR (Processor Version Register) and selects one of our existing CPU specs based on it. This means that the option will not work if the host cpu is not supported by TCG, even if that wouldn't matter for use under kvm. In future, we can extend this in future to override parts of the cpu spec based on information obtained from the host (via /proc/cpuinfo, the host device tree, or explicit KVM calls). That will let us handle cases where the real kvm-virtualized CPU doesn't behave exactly like the TCG-emulated CPU. With appropriate annotation of the CPU specs we'll also then be able to use host cpus under kvm even when there isn't a matching full TCG model. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 David Gibson 提交于
The ppc target contains a ppc_find_by_pvr() function, which looks up a CPU spec based on a PVR (that is, based on the value in the target cpu's Processor Version Register). PVR values contain information on both the cpu model (upper 16 bits, usually) and on the precise revision (low 16 bits, usually). ppc_find_by_pvr, as well as making exact PVR matches, attempts to find "close" PVR matches, when we don't have a CPU spec for the exact revision specified. This sounds like a good idea, execpt that the current logic is completely nonsensical. It seems to assume CPU families are subdivided bit by bit in the PVR in a way they just aren't. Specifically, it requires a match on all bits of the specified pvr up to the last non-zero bit. This has the bizarre effect that when the low bits are simply a sequential revision number (a common though not universal pattern), then odd specified revisions must be matched exactly, whereas even specified revisions will also match the next odd revision, likewise for powers of 4, 8 and so forth. To correctly do inexact matching we'd need to re-organize the table of CPU specs to include a mask showing what PVR range the spec is compatible with (similar to the cputable code in the Linux kernel). For now, just remove the bogosity by only permitting exact PVR matches. That at least makes the matching simple and consistent. If we need inexact matching we can add the necessary per-subfamily masks later. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NAlexander Graf <agraf@suse.de>
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- 06 10月, 2011 3 次提交
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由 Fabien Chouteau 提交于
While working on the emulation of the freescale p2010 (e500v2) I realized that there's no implementation of booke's timers features. Currently mpc8544 uses ppc_emb (ppc_emb_timers_init) which is close but not exactly like booke (for example booke uses different SPR). Signed-off-by: NFabien Chouteau <chouteau@adacore.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Fabien Chouteau 提交于
Signed-off-by: NFabien Chouteau <chouteau@adacore.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 David Gibson 提交于
This patch implements support for the CFAR SPR on POWER7 (Come From Address Register), which snapshots the PC value at the time of a branch or an rfid. The latest powerpc-next kernel also catches it and can show it in xmon or in the signal frames. This works well enough to let recent kernels boot (which otherwise oops on the CFAR access). It hasn't been tested enough to be confident that the CFAR values are actually accurate, but one thing at a time. Signed-off-by: NBen Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NAlexander Graf <agraf@suse.de>
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- 21 8月, 2011 1 次提交
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由 Anthony Liguori 提交于
qemu_malloc/qemu_free no longer exist after this commit. Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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