All systems have an RTC.

The IRQ is hooked up but the model does not use it at this stage. There
is no guest code that uses it, so this limitation is acceptable.
Signed-off-by: NJoel Stanley <joel@jms.id.au>
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 20190618165311.27066-5-clg@kaod.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

The RTC is modeled to provide time and date functionality. It is
initialised at zero to match the hardware.

There is no modelling of the alarm functionality, which includes the IRQ
line. As there is no guest code to exercise this function that is
acceptable for now.
Signed-off-by: NJoel Stanley <joel@jms.id.au>
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 20190618165311.27066-4-clg@kaod.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

This will simplify the definition of new SoCs, like the AST2600 which
should use a slightly different address space and have a different set
of controllers.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Message-id: 20190618165311.27066-3-clg@kaod.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

This will simplify the definition of new SoCs, like the AST2600 which
should use a different CPU and a different IRQ number layout.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Message-id: 20190618165311.27066-2-clg@kaod.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Datasheet for i.MX7 is incorrect and i.MX7's PCI IRQ mapping matches
that of i.MX6:

    * INTD/MSI    122
    * INTC        123
    * INTB        124
    * INTA        125

Fix all of the relevant code to reflect that fact. Needed by latest
Linux kernels.

(Reference: Linux kernel commit 538d6e9d597584e80 from an
NXP employee confirming that the datasheet is incorrect and
with a report of a test against hardware.)
Signed-off-by: NAndrey Smirnov <andrew.smirnov@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
[PMM: added ref to kernel commit confirming the datasheet error]
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

MSI mapping needs to be update when MSI address changes, so add the
code to do so.
Signed-off-by: NAndrey Smirnov <andrew.smirnov@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Acked-by: NMichael S. Tsirkin <mst@redhat.com>
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Expression to calculate update_msi_mapping in code handling writes to
DESIGNWARE_PCIE_MSI_INTR0_ENABLE is missing an ! operator and should
be:

    !!root->msi.intr[0].enable ^ !!val;

so that MSI mapping is updated when enabled transitions from either
"none" -> "any" or "any" -> "none". Since that register shouldn't be
written to very often, change the code to update MSI mapping
unconditionally instead of trying to fix the update_msi_mapping logic.
Signed-off-by: NAndrey Smirnov <andrew.smirnov@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Acked-by: NMichael S. Tsirkin <mst@redhat.com>
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Add no-op/unimplemented PCIE PHY IP block. Needed by new kernels to
use PCIE.
Signed-off-by: NAndrey Smirnov <andrew.smirnov@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Instantiate no-op APBH DMA module. Needed to boot latest Linux kernel.
Signed-off-by: NAndrey Smirnov <andrew.smirnov@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>

Allow cortex-a7 to be used with the virt board; it supports
the v7VE features and there is no reason to deny this type.
Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com>
Message-id: fc5404f7-4d1d-c28f-6e48-d8799c82acc0@web.de
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

This machine correctly defines its default_cpu_type to cortex-m3
and report an error if the user requested another cpu_type,
however it does not exit, and this can confuse users trying
to use another core:

  $ qemu-system-arm -M emcraft-sf2 -cpu cortex-m4 -kernel test-m4.elf
  qemu-system-arm: This board can only be used with CPU cortex-m3-arm-cpu
  [output related to M3 core ...]

The CPU is indeed a M3 core:

  (qemu) info qom-tree
  /machine (emcraft-sf2-machine)
    /unattached (container)
      /device[0] (msf2-soc)
        /armv7m (armv7m)
          /cpu (cortex-m3-arm-cpu)

Add the missing exit() call to return to the shell.
Signed-off-by: NPhilippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: NAlistair Francis <alistair.francis@wdc.com>
Reviewed-by: NEduardo Habkost <ehabkost@redhat.com>
Message-id: 20190617160136.29930-1-philmd@redhat.com
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Fix the condition used to check whether the initrd fits
into RAM; in some cases if an initrd was also passed on
the command line we would get an error stating that it
was too big to fit into RAM after the kernel. Despite the
error the loader continued anyway, though, so also add an
exit(1) when the initrd is actually too big.

Fixes: 852dc64d ("hw/arm/boot: Diagnose layouts that put initrd or
DTB off the end of RAM")
Signed-off-by: NAndrew Jones <drjones@redhat.com>
Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190618125844.4863-1-drjones@redhat.com
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Update ppc64 feature and default CPU
next setsockops() options
Improve "-L" option
Another fix for 5.2-rc1 headers

# gpg: Signature made Wed 26 Jun 2019 13:11:04 BST
# gpg:                using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg:                issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg:                 aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* remotes/vivier2/tags/linux-user-for-4.1-pull-request:
  linux-user: set default PPC64 CPU
  linux-user: update PPC64 HWCAP2 feature list
  linux-user: Add support for setsockopt() options IPV6_<ADD|DROP>_MEMBERSHIP
  linux-user: Add support for setsockopt() option SOL_ALG
  linux-user: emulate msgsnd(), msgrcv() and semtimedop()
  util/path: Do not cache all filenames at startup
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

MIPS queue for June 2016th, 2019

# gpg: Signature made Wed 26 Jun 2019 12:38:58 BST
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-jun-26-2019:
  target/mips: Fix big endian host behavior for interleave MSA instructions
  tests/tcg: target/mips: Fix some test cases for pack MSA instructions
  tests/tcg: target/mips: Add support for MSA MIPS32R6 testings
  tests/tcg: target/mips: Add support for MSA big-endian target testings
  tests/tcg: target/mips: Amend tests for MSA int multiply instructions
  tests/tcg: target/mips: Amend tests for MSA int dot product instructions
  tests/tcg: target/mips: Add tests for MSA move instructions
  tests/tcg: target/mips: Add tests for MSA bit move instructions
  dma/rc4030: Minor code style cleanup
  dma/rc4030: Fix off-by-one error in specified memory region size
  hw/mips/gt64xxx_pci: Align the pci0-mem size
  hw/mips/gt64xxx_pci: Convert debug printf()s to trace events
  hw/mips/gt64xxx_pci: Use qemu_log_mask() instead of debug printf()
  hw/mips/gt64xxx_pci: Fix 'spaces' coding style issues
  hw/mips/gt64xxx_pci: Fix 'braces' coding style issues
  hw/mips/gt64xxx_pci: Fix 'tabs' coding style issues
  hw/mips/gt64xxx_pci: Fix multiline comment syntax
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

* Add FTOIZ/UTOF/QSEED insns
* Fix sync of hflags and swapped args of RRPW_INSERT

# gpg: Signature made Tue 25 Jun 2019 14:05:03 BST
# gpg:                using RSA key 6E636A7E83F2DD0CFA6E6E370AD2C6396B69CA14
# gpg:                issuer "kbastian@mail.uni-paderborn.de"
# gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" [full]
# Primary key fingerprint: 6E63 6A7E 83F2 DD0C FA6E  6E37 0AD2 C639 6B69 CA14

* remotes/bkoppelmann2/tags/pull-tricore-20190625:
  tricore: add QSEED instruction
  tricore: sync ctx.hflags with tb->flags
  tricore: fix RRPW_INSERT instruction
  tricore: add UTOF instruction
  tricore: add FTOIZ instruction
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Xen queue

* Fix build
* xen-block: support feature-large-sector-size
* xen-block: Support IOThread polling for PV shared rings
* Avoid usage of a VLA
* Cleanup Xen headers usage

# gpg: Signature made Mon 24 Jun 2019 16:30:32 BST
# gpg:                using RSA key F80C006308E22CFD8A92E7980CF5572FD7FB55AF
# gpg:                issuer "anthony.perard@citrix.com"
# gpg: Good signature from "Anthony PERARD <anthony.perard@gmail.com>" [marginal]
# gpg:                 aka "Anthony PERARD <anthony.perard@citrix.com>" [marginal]
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 5379 2F71 024C 600F 778A  7161 D8D5 7199 DF83 42C8
#      Subkey fingerprint: F80C 0063 08E2 2CFD 8A92  E798 0CF5 572F D7FB 55AF

* remotes/aperard/tags/pull-xen-20190624:
  xen: Import other xen/io/*.h
  Revert xen/io/ring.h of "Clean up a few header guard symbols"
  xen: Drop includes of xen/hvm/params.h
  xen: Avoid VLA
  xen-bus / xen-block: add support for event channel polling
  xen-bus: allow AioContext to be specified for each event channel
  xen-bus: use a separate fd for each event channel
  xen-block: support feature-large-sector-size
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Block patches:
- The SSH block driver now uses libssh instead of libssh2
- The VMDK block driver gets read-only support for the seSparse
  subformat
- Various fixes

# gpg: Signature made Mon 24 Jun 2019 15:42:56 BST
# gpg:                using RSA key 91BEB60A30DB3E8857D11829F407DB0061D5CF40
# gpg:                issuer "mreitz@redhat.com"
# gpg: Good signature from "Max Reitz <mreitz@redhat.com>" [full]
# Primary key fingerprint: 91BE B60A 30DB 3E88 57D1  1829 F407 DB00 61D5 CF40

* remotes/maxreitz/tags/pull-block-2019-06-24:
  iotests: Fix 205 for concurrent runs
  ssh: switch from libssh2 to libssh
  vmdk: Add read-only support for seSparse snapshots
  vmdk: Reduce the max bound for L1 table size
  vmdk: Fix comment regarding max l1_size coverage
  iotest 134: test cluster-misaligned encrypted write
  blockdev: enable non-root nodes for transaction drive-backup source
  nvme: do not advertise support for unsupported arbitration mechanism
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Fix big endian host behavior for interleave MSA instructions. Previous
fix used TARGET_WORDS_BIGENDIAN instead of HOST_WORDS_BIGENDIAN, which
was a mistake.
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: NAleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1561543629-20327-9-git-send-email-aleksandar.markovic@rt-rk.com>

Fix certian test cases for MSA pack instructions.
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: NAleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1561543629-20327-8-git-send-email-aleksandar.markovic@rt-rk.com>

Add files for MSA MIPS32R6 target testings (copiling and running).
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: NAleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1561543629-20327-7-git-send-email-aleksandar.markovic@rt-rk.com>

Add files for MSA big-endian target testings (copiling and running).

Little-endian files are renamed and ammended too.
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: NAleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1561543629-20327-6-git-send-email-aleksandar.markovic@rt-rk.com>

Amend tests for MSA int multiply instructions.
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: NAleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1561543629-20327-5-git-send-email-aleksandar.markovic@rt-rk.com>

Add tests for instructions whose result depends on the value in destination
register (prior to instruction execution).
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: NAleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1561543629-20327-4-git-send-email-aleksandar.markovic@rt-rk.com>

Add tests for MSA move instructions.
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: NAleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1561543629-20327-3-git-send-email-aleksandar.markovic@rt-rk.com>

Add tests for MSA bit move instructions.
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: NAleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1561543629-20327-2-git-send-email-aleksandar.markovic@rt-rk.com>

Fix some simple checkpatch.pl warnings in rc4030.c.
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: NAleksandar Rikalo <arikalo@wavecomp.com>
Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <1561472838-32272-3-git-send-email-aleksandar.markovic@rt-rk.com>

The size is one byte less than it should be:

address-space: rc4030-dma
  0000000000000000-00000000fffffffe (prio 0, i/o): rc4030.dma

rc4030 is used in MIPS Jazz board context.
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: NAleksandar Rikalo <arikalo@wavecomp.com>
Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: NPhilippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <1561472838-32272-2-git-send-email-aleksandar.markovic@rt-rk.com>

One byte is missing, use an aligned size.

    (qemu) info mtree
    memory-region: pci0-mem
      0000000000000000-00000000fffffffe (prio 0, i/o): pci0-mem
                                      ^
Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <20190624222844.26584-8-f4bug@amsat.org>

Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <20190624222844.26584-7-f4bug@amsat.org>

Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <20190624222844.26584-6-f4bug@amsat.org>

Since we'll move this code around, fix its style first:

  ERROR: space prohibited between function name and open parenthesis
  ERROR: line over 90 characters
Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <20190624222844.26584-5-f4bug@amsat.org>

Since we'll move this code around, fix its style first:

  ERROR: braces {} are necessary for all arms of this statement
Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <20190624222844.26584-4-f4bug@amsat.org>

Since we'll move this code around, fix its style first:

  ERROR: code indent should never use tabs
Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <20190624222844.26584-3-f4bug@amsat.org>

Since commit 8c06fbdf checkpatch.pl enforce a new multiline
comment syntax. Since we'll move this code around, fix its style
first.
Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <20190624222844.26584-2-f4bug@amsat.org>

Signed-off-by: NAndreas Konopik <andreas.konopik@efs-auto.de>
Signed-off-by: NDavid Brenken <david.brenken@efs-auto.de>
Signed-off-by: NGeorg Hofstetter <georg.hofstetter@efs-auto.de>
Signed-off-by: NRobert Rasche <robert.rasche@efs-auto.de>
Signed-off-by: NLars Biermanski <lars.biermanski@efs-auto.de>
Reviewed-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20190624070339.4408-6-david.brenken@efs-auto.org>
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
[BK: Added fp_status arg to float32_is_signaling_nan()]

Signed-off-by: NAndreas Konopik <andreas.konopik@efs-auto.de>
Signed-off-by: NDavid Brenken <david.brenken@efs-auto.de>
Signed-off-by: NGeorg Hofstetter <georg.hofstetter@efs-auto.de>
Signed-off-by: NRobert Rasche <robert.rasche@efs-auto.de>
Signed-off-by: NLars Biermanski <lars.biermanski@efs-auto.de>
Reviewed-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20190624070339.4408-5-david.brenken@efs-auto.org>
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>

Signed-off-by: NAndreas Konopik <andreas.konopik@efs-auto.de>
Signed-off-by: NDavid Brenken <david.brenken@efs-auto.de>
Signed-off-by: NGeorg Hofstetter <georg.hofstetter@efs-auto.de>
Signed-off-by: NRobert Rasche <robert.rasche@efs-auto.de>
Signed-off-by: NLars Biermanski <lars.biermanski@efs-auto.de>
Reviewed-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20190624070339.4408-4-david.brenken@efs-auto.org>
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>

Signed-off-by: NAndreas Konopik <andreas.konopik@efs-auto.de>
Signed-off-by: NDavid Brenken <david.brenken@efs-auto.de>
Signed-off-by: NGeorg Hofstetter <georg.hofstetter@efs-auto.de>
Signed-off-by: NRobert Rasche <robert.rasche@efs-auto.de>
Signed-off-by: NLars Biermanski <lars.biermanski@efs-auto.de>
Reviewed-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20190624070339.4408-3-david.brenken@efs-auto.org>
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>

Signed-off-by: NAndreas Konopik <andreas.konopik@efs-auto.de>
Signed-off-by: NDavid Brenken <david.brenken@efs-auto.de>
Signed-off-by: NGeorg Hofstetter <georg.hofstetter@efs-auto.de>
Signed-off-by: NRobert Rasche <robert.rasche@efs-auto.de>
Signed-off-by: NLars Biermanski <lars.biermanski@efs-auto.de>
Reviewed-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20190624070339.4408-2-david.brenken@efs-auto.org>
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>

The default CPU for pseries has been set to POWER9 by default.
We can use the same default for linux-user
Signed-off-by: NLaurent Vivier <laurent@vivier.eu>
Message-Id: <20190609143521.19374-2-laurent@vivier.eu>
Signed-off-by: NLaurent Vivier <laurent@vivier.eu>