- 23 9月, 2016 40 次提交
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由 Peter Maydell 提交于
* More KVM LAPIC fixes * fix divide-by-zero regression on libiscsi SG devices * fix qemu-char segfault * add scripts/show-fixed-bugs.sh # gpg: Signature made Thu 22 Sep 2016 19:20:57 BST # gpg: using RSA key 0xBFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: kvm: fix events.flags (KVM_VCPUEVENT_VALID_SMM) overwritten by 0 scripts: Add a script to check for bug URLs in the git log msmouse: Fix segfault caused by free the chr before chardev cleanup. iscsi: Fix divide-by-zero regression on raw SG devices kvm: apic: set APIC base as part of kvm_apic_put target-i386: introduce kvm_put_one_msr Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Herongguang (Stephen) 提交于
Fix events.flags (KVM_VCPUEVENT_VALID_SMM) overwritten by 0. Signed-off-by: NHe Rongguang <herongguang.he@huawei.com> Message-Id: <57E38EAC.3020108@huawei.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Thomas Huth 提交于
Basic idea of this script is to check the git log for URLs to the QEMU bugtracker at launchpad.net and to figure out whether the related bug has been marked there as "Fix released" (i.e. closed) already. So this script can e.g. be used after each public release of QEMU to check whether there are any bug tickets that could be moved from "Fix committed" (or another state if the author of the patch forgot to update the bug ticket) to "Fix released". Signed-off-by: NThomas Huth <thuth@redhat.com> Message-Id: <1474486942-18754-1-git-send-email-thuth@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Lin Ma 提交于
Segfault happens when leaving qemu with msmouse backend: #0 0x00007fa8526ac975 in raise () at /lib64/libc.so.6 #1 0x00007fa8526add8a in abort () at /lib64/libc.so.6 #2 0x0000558be78846ab in error_exit (err=16, msg=0x558be799da10 ... #3 0x0000558be7884717 in qemu_mutex_destroy (mutex=0x558be93be750) at ... #4 0x0000558be7549951 in qemu_chr_free_common (chr=0x558be93be750) at ... #5 0x0000558be754999c in qemu_chr_free (chr=0x558be93be750) at ... #6 0x0000558be7549a20 in qemu_chr_delete (chr=0x558be93be750) at ... #7 0x0000558be754a8ef in qemu_chr_cleanup () at qemu-char.c:4643 #8 0x0000558be755843e in main (argc=5, argv=0x7ffe925d7118, ... The chr was freed by msmouse close callback before chardev cleanup, Then qemu_mutex_destroy triggered raise(). Because freeing chr is handled by qemu_chr_free_common, Remove the free from msmouse_chr_close to avoid double free. Fixes: c1111a24 Cc: qemu-stable@nongnu.org Signed-off-by: NLin Ma <lma@suse.com> Message-Id: <20160915143158.4796-1-lma@suse.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Eric Blake 提交于
When qemu uses iscsi devices in sg mode, iscsilun->block_size is left at 0. Prior to commits cf081fca and similar, when block limits were tracked in sectors, this did not matter: various block limits were just left at 0. But when we started scaling by block size, this caused SIGFPE. Then, in a later patch, commit a5b8dd2c added an assertion to bdrv_open_common() that request_alignment is always non-zero; which was not true for SG mode. Rather than relax that assertion, we can just provide a sane value (we don't know of any SG device with a block size smaller than qemu's default sizing of 512 bytes). One possible solution for SG mode is to just blindly skip ALL of iscsi_refresh_limits(), since we already short circuit so many other things in sg mode. But this patch takes a slightly more conservative approach, and merely guarantees that scaling will succeed, while still using multiples of the original size where possible. Resulting limits may still be zero in SG mode (that is, we mostly only fix block_size used as a denominator or which affect assertions, not all uses). Reported-by: NHolger Schranz <holger@fam-schranz.de> Signed-off-by: NEric Blake <eblake@redhat.com> CC: qemu-stable@nongnu.org Message-Id: <1473283640-15756-1-git-send-email-eblake@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Peter Maydell 提交于
target-arm queue: * add Cortex-A7 CPU * new ast2500 SoC model and evaluation board * palmetto-bmc: remove stray double assignment * aspeed: clean up RAM size handling * ptimer: framework for defining policy bits to change behaviour choices for different timer devices * ptimer: add some test cases * cadence_gem: add queue support * loader: support loading images to specified address spaces * loader: support auto-detect of ELF architecture from file * dma: xlnx-zynq-devcfg: Fix up XLNX_ZYNQ_DEVCFG_R_MAX * vmstateify ssd0323 * vmstateify ssi-sd * disas/arm.c: remove unused macros * imx: use 'const char', not 'char const' # gpg: Signature made Thu 22 Sep 2016 18:20:22 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20160922: (36 commits) imx: Use 'const char', not 'char const' disas/arm.c: Remove unused macro definitions vmstateify ssi-sd vmstateify ssd0323 display dma: xlnx-zynq-devcfg: Fix up XLNX_ZYNQ_DEVCFG_R_MAX loader: Add AddressSpace loading support to targphys loader: Add AddressSpace loading support to uImages loader: Add AddressSpace loading support to ELFs loader: Allow a custom AddressSpace when loading ROMs loader: Use the specified MemoryRegion loader: Allow ELF loader to auto-detect the ELF arch xlnx-zynqmp: Set the number of priority queues cadence_gem: Correct indentation cadence_gem: Add queue support cadence_gem: Add support for screening cadence_gem: Add the num-priority-queues property cadence_gem: QOMify Cadence GEM tests: Add ptimer tests hw/ptimer: Suppress error messages under qtest hw/ptimer: Introduce timer policy feature ... Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
'char const' means the same thing as 'const char', but we use the former in only a handful of places and we use the latter over six thousand times. Switch the imx reg_name() functions to bring them in line with everything else. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
The macros ISSPACE, strneq, NUM_ELEMS and NUM_ARM_REGNAMES are defined in disas/arm.c but never used. Remove the unnecessary definitions. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Dr. David Alan Gilbert 提交于
Changed a few types to fixed sized types in the ssi_sd_state Now saving/loading a byte for the cmdarg/response bytes that were previously saved as uint32 Bumped version number to deal with those changes. Signed-off-by: NDr. David Alan Gilbert <dgilbert@redhat.com> Message-id: 1472035246-12483-4-git-send-email-dgilbert@redhat.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Dr. David Alan Gilbert 提交于
Bumps version number because we now use the VMSTATE_SSI_SLAVE that only uses a byte rather than a 32bit (for saving a bool 'cs'). Signed-off-by: NDr. David Alan Gilbert <dgilbert@redhat.com> Message-id: 1472035246-12483-2-git-send-email-dgilbert@redhat.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Nathan Rossi 提交于
Whilst according to the Zynq TRM this device covers a register region of 0x000 - 0x120. The register region is also shared with XADCIF prefix registers at 0x100 and above. Due to how the devcfg and the xadc devices are implemented in QEMU these are separate models with individual mmio regions. As such the region registered by the devcfg overlaps with the xadc when initialized in a machine model (e.g. xilinx-zynq-a9). This patch fixes up the incorrect region size, where XLNX_ZYNQ_DEVCFG_R_MAX is missing its '/ 4' causing it to be 0x460 in size. As well as setting the region size to the 0x0 - 0x100 region so that an xadc device instance can be registered in the correct region to pair with the devcfg device instance. Mapping with XLNX_ZYNQ_DEVCFG_R_MAX = 0x118: dev: xlnx.ps7-dev-cfg, id "" mmio 00000000f8007000/0000000000000460 dev: xlnx,zynq-xadc, id "" mmio 00000000f8007100/0000000000000020 Mapping with XLNX_ZYNQ_DEVCFG_R_MAX = 0x100 / 4: dev: xlnx.ps7-dev-cfg, id "" mmio 00000000f8007000/0000000000000100 dev: xlnx,zynq-xadc, id "" mmio 00000000f8007100/0000000000000020 Signed-off-by: NNathan Rossi <nathan@nathanrossi.com> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Message-id: 20160921180911.32289-1-nathan@nathanrossi.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
Add a new function load_image_targphys_as() that allows the caller to specify an AddressSpace to use when loading a targphys. The original load_image_targphys() function doesn't have any change in functionality. Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 87de45de7acf02cbe6bae9d6c4d6fb8f3aba4f61.1474331683.git.alistair.francis@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
Add a new function load_uimage_as() that allows the caller to specify an AddressSpace to use when loading the uImage. The original load_uimage() function doesn't have any change in functionality. Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1254092e6b80d3cd3cfabafe165d56a96c54c0b5.1474331683.git.alistair.francis@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
Add a new function load_elf_as() that allows the caller to specify an AddressSpace to use when loading the ELF. The original load_elf() function doesn't have any change in functionality. Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 8b5cefecdf56fba4ccdff2db880f0b6b264cf16f.1474331683.git.alistair.francis@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
When loading ROMs allow the caller to specify an AddressSpace to use for the load. Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Message-id: 85f86b94ea94879e7ce8b12e85ac8de26658f7eb.1474331683.git.alistair.francis@xilinx.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
Prevously the specified MemoryRegion was ignored during the rom register reset. This patch uses the rom MemoryRegion is avaliable. Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: d63fef5524deeb88e0068ca9d3fd4c8344f54dd4.1474331683.git.alistair.francis@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
If the caller didn't specify an architecture for the ELF machine the load_elf() function will auto detect it based on the ELF file. Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: f2d70b47fcad31445f947f8817a0e146d80a046b.1474331683.git.alistair.francis@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
Set the ZynqMP number of priority queues to 2. Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: e047c338ee981a61afd7f765a317b3de25a4f629.1469727764.git.alistair.francis@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
Fix up the indentation inside the for loop that was introduced in the previous patch. This commit is almost empty if viewed using 'git show -w', except for a few changes that were required to avoid the 80 charecter line limit. Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: b40d1b12d24be9f0ac5d72f86249103e0c1c720a.1469727764.git.alistair.francis@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 28921252217b1d14f16889bafa88675f5b7a66cb.1469727764.git.alistair.francis@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
The Cadence GEM hardware allows incoming data to be 'screened' based on some register values. Add support for these screens. We also need to increase the max regs to avoid compilation failures. These new registers are implemented in the next patch. Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 73e69a8ad9fa2763e9f68f71eaf2469dd5744fcc.1469727764.git.alistair.francis@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
The Cadence GEM hardware supports N number priority queues, this patch is a step towards that by adding the property to set the queues. At the moment behaviour doesn't change as we only use queue 0. Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 6543ec0d0c4bfd2678d0ed683efb197e91b17733.1469727764.git.alistair.francis@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
The sysbus_init_irq() call will eventually depend on a property so it needs to be in the realize function. Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 486595809cf416d18a750aafbcfa1c81d7160c59.1469727764.git.alistair.francis@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Dmitry Osipenko 提交于
Ptimer is a generic countdown timer helper that is used by many timer device models as well as by the QEMU core. Add QTests for the ptimer. Signed-off-by: NDmitry Osipenko <digetx@gmail.com> Message-id: 1de89fe6e1ccaf6c8071ee3469e1a844df948359.1473252818.git.digetx@gmail.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Dmitry Osipenko 提交于
Under qtest ptimer emits lots of warning messages. The messages are caused by the actual checking of the ptimer error conditions. Suppress those messages, so they do not distract. Signed-off-by: NDmitry Osipenko <digetx@gmail.com> Message-id: 44877fff4ff03205590698d3dc189ad6d091472f.1473252818.git.digetx@gmail.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Dmitry Osipenko 提交于
Some of the timer devices may behave differently from what ptimer provides. Introduce ptimer policy feature that allows ptimer users to change default and wrong timer behaviour, for example to continuously trigger periodic timer when load value is equal to "0". Signed-off-by: NDmitry Osipenko <digetx@gmail.com> Message-id: 994cd608ec392da6e58f0643800dda595edb9d97.1473252818.git.digetx@gmail.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Dmitry Osipenko 提交于
Running with counter / period = 0 is treated as a error case, printing error message claiming that timer has been disabled. However, timer is only marked as disabled, keeping to tick till expired and triggering after being claimed as disabled. Stop the QEMU timer to avoid confusion. Signed-off-by: NDmitry Osipenko <digetx@gmail.com> Message-id: 1e9bae4fae3c36430d7c28b0f486a0c71aff7eb3.1473252818.git.digetx@gmail.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
If the RAM size is invalid, the memory controller will use a default value. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1473438177-26079-15-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
Configure the size of the RAM of the SOC using a property to propagate the value down to the memory controller from the board level. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1473438177-26079-14-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
Also change the default value used in case of an error. The minimum size is a bit severe, so let's just use an average RAM size. Signed-off-by: NCédric Le Goater <clg@kaod.org> Message-id: 1473438177-26079-13-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
There is no need to do this at each reset as the RAM size will not change. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1473438177-26079-12-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1473438177-26079-11-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
The ast2500 eval board has a hardware strapping register value of 0xF100C2E6 which we use for a definition of AST2500_EVB_HW_STRAP1 below. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1473438177-26079-10-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
Based on previous work done by Andrew Jeffery <andrew@aj.id.au>. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1473438177-26079-9-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
This gives some explanation behind the magic number 0x120CE416. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1473438177-26079-8-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
aspeed_board_init() now uses a board identifier to customize some values specific to the board. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1473438177-26079-7-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
This is mostly a name replacement to prepare ground for other SoCs specificities. It also adds a TypeInfo struct for the palmetto-bmc board with a custom initialization for the same reason. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1473438177-26079-6-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
We plan to add more Aspeed boards to this file. There are no changes in the code. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1473438177-26079-5-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
Let's define an object class for each Aspeed SoC we support. A AspeedSoCInfo struct gathers the SoC specifications which can later be used by an instance of the class or by a board using the SoC. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1473438177-26079-4-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
This is a name replacement to prepare ground for other SoCs. Let's also remove the AST2400_SMC_BASE definition from the address space mappings, as it is not used. This controller was removed from the Aspeed SoC AST2500, so this provides us a better common base for the address space mapping on both SoCs. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1473438177-26079-3-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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