- 30 4月, 2019 5 次提交
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由 Peter Maydell 提交于
The M-profile FPCCR.S bit indicates the security status of the floating point context. In the pseudocode ExecuteFPCheck() function it is unconditionally set to match the current security state whenever a floating point instruction is executed. Implement this by adding a new TB flag which tracks whether FPCCR.S is different from the current security state, so that we only need to emit the code to update it in the less-common case when it is not already set correctly. Note that we will add the handling for the other work done by ExecuteFPCheck() in later commits. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190416125744.27770-19-peter.maydell@linaro.org
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由 Peter Maydell 提交于
We are close to running out of TB flags for AArch32; we could start using the cs_base word, but before we do that we can economise on our usage by sharing the same bits for the VFP VECSTRIDE field and the XScale XSCALE_CPAR field. This works because no XScale CPU ever had VFP. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190416125744.27770-18-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Move the NS TBFLAG down from bit 19 to bit 6, which has not been used since commit c1e37810 in 2015, when we started passing the entire MMU index in the TB flags rather than just a 'privilege level' bit. This rearrangement is not strictly necessary, but means that we can put M-profile-only bits next to each other rather than scattered across the flag word. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190416125744.27770-17-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Implement the code which updates the FPCCR register on an exception entry where we are going to use lazy FP stacking. We have to defer to the NVIC to determine whether the various exceptions are currently ready or not. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20190416125744.27770-12-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The M-profile floating point support has three associated config registers: FPCAR, FPCCR and FPDSCR. It also makes the registers CPACR and NSACR have behaviour other than reads-as-zero. Add support for all of these as simple reads-as-written registers. We will hook up actual functionality later. The main complexity here is handling the FPCCR register, which has a mix of banked and unbanked bits. Note that we don't share storage with the A-profile cpu->cp15.nsacr and cpu->cp15.cpacr_el1, though the behaviour is quite similar, for two reasons: * the M profile CPACR is banked between security states * it preserves the invariant that M profile uses no state inside the cp15 substruct Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190416125744.27770-4-peter.maydell@linaro.org
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- 19 4月, 2019 2 次提交
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由 Markus Armbruster 提交于
CPUClass method dump_statistics() takes an fprintf()-like callback and a FILE * to pass to it. Most callers pass fprintf() and stderr. log_cpu_state() passes fprintf() and qemu_log_file. hmp_info_registers() passes monitor_fprintf() and the current monitor cast to FILE *. monitor_fprintf() casts it right back, and is otherwise identical to monitor_printf(). The callback gets passed around a lot, which is tiresome. The type-punning around monitor_fprintf() is ugly. Drop the callback, and call qemu_fprintf() instead. Also gets rid of the type-punning, since qemu_fprintf() takes NULL instead of the current monitor cast to FILE *. Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Reviewed-by: NDr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20190417191805.28198-15-armbru@redhat.com>
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由 Markus Armbruster 提交于
The various TARGET_cpu_list() take an fprintf()-like callback and a FILE * to pass to it. Their callers (vl.c's main() via list_cpus(), bsd-user/main.c's main(), linux-user/main.c's main()) all pass fprintf() and stdout. Thus, the flexibility provided by the (rather tiresome) indirection isn't actually used. Drop the callback, and call qemu_printf() instead. Calling printf() would also work, but would make the code unsuitable for monitor context without making it simpler. Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Message-Id: <20190417191805.28198-10-armbru@redhat.com> Reviewed-by: NDr. David Alan Gilbert <dgilbert@redhat.com>
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- 25 3月, 2019 1 次提交
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由 Andrew Jones 提交于
These functions are not used outside helper.c Signed-off-by: NAndrew Jones <drjones@redhat.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190322162333.17159-4-drjones@redhat.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 05 3月, 2019 6 次提交
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由 Richard Henderson 提交于
Tested-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190301200501.16533-11-richard.henderson@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Tested-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190301200501.16533-9-richard.henderson@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Tested-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190301200501.16533-8-richard.henderson@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> [PMM: fixed up block comment style] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190301200501.16533-4-richard.henderson@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190301200501.16533-3-richard.henderson@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Minimize the number of places that will need updating when the virtual host extensions are added. Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190301200501.16533-2-richard.henderson@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 28 2月, 2019 5 次提交
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由 Richard Henderson 提交于
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190219222952.22183-4-richard.henderson@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190219222952.22183-3-richard.henderson@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
This reverts commit 823e1b38, which introduces a regression running EDK2 guest firmware under KVM: error: kvm run failed Function not implemented PC=000000013f5a6208 X00=00000000404003c4 X01=000000000000003a X02=0000000000000000 X03=00000000404003c4 X04=0000000000000000 X05=0000000096000046 X06=000000013d2ef270 X07=000000013e3d1710 X08=09010755ffaf8ba8 X09=ffaf8b9cfeeb5468 X10=feeb546409010756 X11=09010757ffaf8b90 X12=feeb50680903068b X13=090306a1ffaf8bc0 X14=0000000000000000 X15=0000000000000000 X16=000000013f872da0 X17=00000000ffffa6ab X18=0000000000000000 X19=000000013f5a92d0 X20=000000013f5a7a78 X21=000000000000003a X22=000000013f5a7ab2 X23=000000013f5a92e8 X24=000000013f631090 X25=0000000000000010 X26=0000000000000100 X27=000000013f89501b X28=000000013e3d14e0 X29=000000013e3d12a0 X30=000000013f5a2518 SP=000000013b7be0b0 PSTATE=404003c4 -Z-- EL1t with [ 3507.926571] kvm [35042]: load/store instruction decoding not implemented in the host dmesg. Revert the change for the moment until we can investigate the cause of the regression. Reported-by: NEric Auger <eric.auger@redhat.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
There is a set of VFP instructions which we implement in disas_vfp_v8_insn() and gate on the ARM_FEATURE_V8 bit. These were all first introduced in v8 for A-profile, but in M-profile they appeared in v7M. Gate them on the MVFR2 FPMisc field instead, and rename the function appropriately. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190222170936.13268-3-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Instead of gating the A32/T32 FP16 conversion instructions on the ARM_FEATURE_VFP_FP16 flag, switch to our new approach of looking at ID register bits. In this case MVFR1 fields FPHP and SIMDHP indicate the presence of these insns. This change doesn't alter behaviour for any of our CPUs. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190222170936.13268-2-peter.maydell@linaro.org
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- 22 2月, 2019 1 次提交
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由 Richard Henderson 提交于
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190215192302.27855-5-richard.henderson@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> [PMM: fixed a couple of comment typos] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 15 2月, 2019 5 次提交
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由 Richard Henderson 提交于
Change the representation of this field such that it is easy to set from vector code. Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-11-richard.henderson@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
At the moment the Arm implementations of kvm_arch_{get,put}_registers() don't support having QEMU change the values of system registers (aka coprocessor registers for AArch32). This is because although kvm_arch_get_registers() calls write_list_to_cpustate() to update the CPU state struct fields (so QEMU code can read the values in the usual way), kvm_arch_put_registers() does not call write_cpustate_to_list(), meaning that any changes to the CPU state struct fields will not be passed back to KVM. The rationale for this design is documented in a comment in the AArch32 kvm_arch_put_registers() -- writing the values in the cpregs list into the CPU state struct is "lossy" because the write of a register might not succeed, and so if we blindly copy the CPU state values back again we will incorrectly change register values for the guest. The assumption was that no QEMU code would need to write to the registers. However, when we implemented debug support for KVM guests, we broke that assumption: the code to handle "set the guest up to take a breakpoint exception" does so by updating various guest registers including ESR_EL1. Support this by making kvm_arch_put_registers() synchronize CPU state back into the list. We sync only those registers where the initial write succeeds, which should be sufficient. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Tested-by: NAlex Bennée <alex.bennee@linaro.org> Tested-by: NDongjiu Geng <gengdongjiu@huawei.com>
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由 Alex Bennée 提交于
There are a whole bunch more registers in the CPUID space which are currently not used but are exposed as RAZ. To avoid too much duplication we expand ARMCPRegUserSpaceInfo to understand glob patterns so we only need one entry to tweak whole ranges of registers. Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 20190205190224.2198-5-alex.bennee@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alex Bennée 提交于
A number of CPUID registers are exposed to userspace by modern Linux kernels thanks to the "ARM64 CPU Feature Registers" ABI. For QEMU's user-mode emulation we don't need to emulate the kernels trap but just return the value the trap would have done. To avoid too much #ifdef hackery we process ARMCPRegInfo with a new helper (modify_arm_cp_regs) before defining the registers. The modify routine is driven by a simple data structure which describes which bits are exported and which are fixed. Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 20190205190224.2198-3-alex.bennee@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alex Bennée 提交于
Although technically not visible to userspace the kernel does make them visible via a trap and emulate ABI. We provide a new permission mask (PL0U_R) which maps to PL0_R for CONFIG_USER builds and adjust the minimum permission check accordingly. Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 20190205190224.2198-2-alex.bennee@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 06 2月, 2019 5 次提交
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由 Peter Maydell 提交于
The {IOE, DZE, OFE, UFE, IXE, IDE} bits in the FPSCR/FPCR are for enabling trapped IEEE floating point exceptions (where IEEE exception conditions cause a CPU exception rather than updating the FPSR status bits). QEMU doesn't implement this (and nor does the hardware we're modelling), but for implementations which don't implement trapped exception handling these control bits are supposed to be RAZ/WI. This allows guest code to test for whether the feature is present by trying to write to the bit and checking whether it sticks. QEMU is incorrectly making these bits read as written. Make them RAZ/WI as the architecture requires. In particular this was causing problems for the NetBSD automatic test suite. Reported-by: NMartin Husemann <martin@netbsd.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190131130700.28392-1-peter.maydell@linaro.org
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由 Richard Henderson 提交于
Split out gen_top_byte_ignore in preparation of handling these data accesses; the new tbflags field is not yet honored. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190204132126.3255-2-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190128223118.5255-4-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Place this in its own field within ENV, as that will make it easier to reset from within TCG generated code. With the change to pstate_read/write, exception entry and return are automatically handled. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190128223118.5255-3-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Also create field definitions for id_aa64pfr1 from ARMv8.5. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190128223118.5255-2-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 01 2月, 2019 2 次提交
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由 Remi Denis-Courmont 提交于
Since QEMU does not support the ARMv8.2-LVA, Large Virtual Address, extension (yet), the VA address space is 48-bits plus a sign bit. User mode can only handle the positive half of the address space, so that makes a limit of 48 bits. (With LVA, it would be 53 and 52 bits respectively.) The incorrectly large address space conflicts with PAuth instructions, which use bits 48-54 and 56-63 for the pointer authentication code. This also conflicts with (as yet unsupported by QEMU) data tagging and with the ARMv8.5-MTE extension. Signed-off-by: NRemi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Aaron Lindsay OS 提交于
Make PMU overflow interrupts more accurate by using a timer to predict when they will overflow rather than waiting for an event to occur which allows us to otherwise check them. Signed-off-by: NAaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190124162401.5111-3-aaron@os.amperecomputing.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 29 1月, 2019 1 次提交
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由 Aaron Lindsay OS 提交于
A bug was introduced during a respin of: commit 57a4a11b target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 This patch introduced two calls to get_pmceid() during CPU initialization - one each for PMCEID0 and PMCEID1. In addition to building the register values, get_pmceid() clears an internal array mapping event numbers to their implementations (supported_event_map) before rebuilding it. This is an optimization since much of the logic is shared. However, since it was called twice, the contents of supported_event_map reflect only the events in PMCEID1 (the second call to get_pmceid()). Fix this bug by moving the initialization of PMCEID0 and PMCEID1 back into a single function call, and name it more appropriately since it is doing more than simply generating the contents of the PMCEID[01] registers. Signed-off-by: NAaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190123195814.29253-1-aaron@os.amperecomputing.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 21 1月, 2019 7 次提交
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由 Aaron Lindsay 提交于
Add arrays to hold the registers, the definitions themselves, access functions, and logic to reset counters when PMCR.P is set. Update filtering code to support counters other than PMCCNTR. Support migration with raw read/write functions. Signed-off-by: NAaron Lindsay <alindsay@codeaurora.org> Signed-off-by: NAaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20181211151945.29137-11-aaron@os.amperecomputing.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Aaron Lindsay 提交于
This commit doesn't add any supported events, but provides the framework for adding them. We store the pm_event structs in a simple array, and provide the mapping from the event numbers to array indexes in the supported_event_map array. Because the value of PMCEID[01] depends upon which events are supported at runtime, generate it dynamically. Signed-off-by: NAaron Lindsay <alindsay@codeaurora.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-10-aaron@os.amperecomputing.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Aaron Lindsay 提交于
Signed-off-by: NAaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-9-aaron@os.amperecomputing.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Aaron Lindsay 提交于
This is immediately necessary for the PMUv3 implementation to check ID_DFR0.PerfMon to enable/disable specific features, but defines the full complement of fields for possible future use elsewhere. Signed-off-by: NAaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-8-aaron@os.amperecomputing.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Aaron Lindsay 提交于
Rename arm_ccnt_enabled to pmu_counter_enabled, and add logic to only return 'true' if the specified counter is enabled and neither prohibited or filtered. Signed-off-by: NAaron Lindsay <alindsay@codeaurora.org> Signed-off-by: NAaron Lindsay <aclindsa@gmail.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20181211151945.29137-5-aaron@os.amperecomputing.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Aaron Lindsay 提交于
pmccntr_read and pmccntr_write contained duplicate code that was already being handled by pmccntr_sync. Consolidate the duplicated code into two functions: pmccntr_op_start and pmccntr_op_finish. Add a companion to c15_ccnt in CPUARMState so that we can simultaneously save both the architectural register value and the last underlying cycle count - this ensures time isn't lost and will also allow us to access the 'old' architectural register value in order to detect overflows in later patches. Signed-off-by: NAaron Lindsay <alindsay@codeaurora.org> Signed-off-by: NAaron Lindsay <aclindsa@gmail.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-3-aaron@os.amperecomputing.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
The arm_regime_tbi{0,1} functions are replacable with the new function by giving the lowest and highest address. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-24-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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