- 04 1月, 2017 9 次提交
-
-
由 Greg Kurz 提交于
This patch lays the foundations to be able to test 9P operations and provides a test for the version operation as a first example. A 9P request is composed of a T-message sent by the client (guest) to the server (QEMU), and a R-message sent by the server back to the client. The following general calls are available to implement requests for any 9P operations: v9fs_req_init(): allocates the request structure and the guest memory for the T-message v9fs_req_send(): allocates the guest memory for the R-message and sends the T-message to QEMU v9fs_req_recv(): waits for QEMU to answer and does some sanity checks on the returned R-message header v9fs_req_free(): releases the guest memory and the request structure Helpers are provided, to be used by each specific 9P operation to copy data to/from the guest memory. The version operation is used to negotiate the 9P protocol version to be used and the maximum buffer size for exchanged data. It is necessarily the first message of a 9P session. For simplicity, the maximum buffer size is hardcoded to 4k, which should be enough for functional tests. The test simply advertises the "9P2000.L" version to QEMU and expects QEMU to answer it is supported. References: http://man.cat-v.org/plan_9/5/intro http://man.cat-v.org/plan_9/5/versionSigned-off-by: NGreg Kurz <groug@kaod.org>
-
由 Greg Kurz 提交于
The u16 and u32 types don't exist in QEMU common headers. It never broke build because these two macros aren't use by the current code, but this is about to change with the future addition of functional tests for 9P. Also, these should have enclosing parenthesis to be usable in any syntactical situation. As suggested by Eric Blake, let's use UINT16_MAX and UINT32_MAX to address both issues. Signed-off-by: NGreg Kurz <groug@kaod.org>
-
由 Greg Kurz 提交于
This moves the test_share static and the QOSState into the QVirtIO9P structure, and put PCI related code in functions with a _pci_ name. This will avoid code duplication in future tests, and allow to add support for non-PCI platforms. Signed-off-by: NGreg Kurz <groug@kaod.org>
-
由 Greg Kurz 提交于
Signed-off-by: NGreg Kurz <groug@kaod.org>
-
由 Greg Kurz 提交于
If the user passes -device virtio-9p without the corresponding -fsdev, QEMU dereferences a NULL pointer and crashes. This is a 2.8 regression introduced by commit 702dbcc2. Signed-off-by: NGreg Kurz <groug@kaod.org> Reviewed-by: NLi Qiang <liq3ea@gmail.com>
-
由 Stefano Stabellini 提交于
Not all 9pfs transports share memory between request and response. For those who don't, it is necessary to know how much memory is required in the response. Split the existing init_iov_from_pdu function in two: init_out_iov_from_pdu (for writes) and init_in_iov_from_pdu (for reads). init_in_iov_from_pdu takes an additional size parameter to specify the memory required for the response message. Signed-off-by: NStefano Stabellini <sstabellini@kernel.org> Reviewed-by: NGreg Kurz <groug@kaod.org> Signed-off-by: NGreg Kurz <groug@kaod.org>
-
由 Stefano Stabellini 提交于
v9fs_xattr_read should not access VirtQueueElement elems directly. Move v9fs_init_qiov_from_pdu up in the file and call v9fs_init_qiov_from_pdu before v9fs_pack. Use v9fs_pack on the new iovec. Signed-off-by: NStefano Stabellini <sstabellini@kernel.org> Reviewed-by: NGreg Kurz <groug@kaod.org> Signed-off-by: NGreg Kurz <groug@kaod.org>
-
由 Stefano Stabellini 提交于
Don't call virtio functions from 9pfs generic code, use generic function callbacks instead. Signed-off-by: NStefano Stabellini <sstabellini@kernel.org> Reviewed-by: NGreg Kurz <groug@kaod.org> Signed-off-by: NGreg Kurz <groug@kaod.org>
-
由 Stefano Stabellini 提交于
pdus are initialized and used in 9pfs common code. Move the array from V9fsVirtioState to V9fsState. Signed-off-by: NStefano Stabellini <sstabellini@kernel.org> Reviewed-by: NGreg Kurz <groug@kaod.org> Signed-off-by: NGreg Kurz <groug@kaod.org>
-
- 29 12月, 2016 1 次提交
-
-
由 Peter Maydell 提交于
# gpg: Signature made Tue 27 Dec 2016 17:52:12 GMT # gpg: using RSA key 0xF30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" # gpg: aka "Laurent Vivier <laurent@vivier.eu>" # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/m68k-for-2.9-pull-request: target-m68k: free TCG variables that are not target-m68k: add rol/ror/roxl/roxr instructions target-m68k: Inline shifts target-m68k: Do not cpu_abort on undefined insns target-m68k: Implement 680x0 movem target-m68k: add cas/cas2 ops target-m68k: add abcd/sbcd/nbcd target-m68k: add 680x0 divu/divs variants target-m68k: add 64bit mull target-m68k: add cmpm target-m68k: Split gen_lea and gen_ea target-m68k: Delay autoinc writeback Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
- 28 12月, 2016 13 次提交
-
-
由 Laurent Vivier 提交于
This is a cleanup patch. It adds call to tcg_temp_free() when it is missing. Signed-off-by: NLaurent Vivier <laurent@vivier.eu> Reviewed-by: NRichard Henderson <rth@twiddle.net>
-
由 Laurent Vivier 提交于
Signed-off-by: NLaurent Vivier <laurent@vivier.eu> Reviewed-by: NRichard Henderson <rth@twiddle.net>
-
由 Richard Henderson 提交于
Also manage word and byte operands and fix the computation of overflow in the case of M68000 arithmetic shifts. Signed-off-by: NLaurent Vivier <laurent@vivier.eu> Signed-off-by: NRichard Henderson <rth@twiddle.net> Message-Id: <1478699171-10637-4-git-send-email-rth@twiddle.net>
-
由 Richard Henderson 提交于
Report this properly via exception and, importantly, allow the disassembler the chance to tell us what insn is not handled. Reviewed-by: NLaurent Vivier <laurent@vivier.eu> Signed-off-by: NRichard Henderson <rth@twiddle.net> Message-Id: <1478699171-10637-3-git-send-email-rth@twiddle.net> Signed-off-by: NLaurent Vivier <laurent@vivier.eu>
-
由 Laurent Vivier 提交于
680x0 movem can load/store words and long words and can use more addressing modes. Coldfire can only use long words with (Ax) and (d16,Ax) addressing modes. Signed-off-by: NLaurent Vivier <laurent@vivier.eu> Signed-off-by: NRichard Henderson <rth@twiddle.net> Message-Id: <1478699171-10637-2-git-send-email-rth@twiddle.net>
-
由 Laurent Vivier 提交于
Implement CAS using cmpxchg. Implement CAS2 using helper and either cmpxchg when the 32bit addresses are consecutive, or with parallel_cpus+cpu_loop_exit_atomic() otherwise. Suggested-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NLaurent Vivier <laurent@vivier.eu> Reviewed-by: NRichard Henderson <rth@twiddle.net>
-
由 Laurent Vivier 提交于
Signed-off-by: NLaurent Vivier <laurent@vivier.eu> Reviewed-by: NRichard Henderson <rth@twiddle.net>
-
由 Laurent Vivier 提交于
Update helper to set the throwing location in case of div-by-0. Cleanup divX.w and add quad word variants of divX.l. Signed-off-by: NLaurent Vivier <laurent@vivier.eu> Reviewed-by: NRichard Henderson <rth@twidle.net> [laurent: modified to clear Z on overflow, as found with risu]
-
由 Laurent Vivier 提交于
Signed-off-by: NLaurent Vivier <laurent@vivier.eu> Reviewed-by: NRichard Henderson <rth@twidle.net>
-
由 Laurent Vivier 提交于
Signed-off-by: NLaurent Vivier <laurent@vivier.eu> Reviewed-by: NRichard Henderson <rth@twiddle.net> Message-Id: <1477604609-2206-2-git-send-email-laurent@vivier.eu> Signed-off-by: NRichard Henderson <rth@twiddle.net> Message-Id: <1478206203-4606-4-git-send-email-rth@twiddle.net>
-
由 Richard Henderson 提交于
Provide gen_lea_mode and gen_ea_mode, where the mode can be specified manually, rather than taken from the instruction. Signed-off-by: NRichard Henderson <rth@twiddle.net> Message-Id: <1478206203-4606-3-git-send-email-rth@twiddle.net>
-
由 Richard Henderson 提交于
Signed-off-by: NRichard Henderson <rth@twiddle.net> Message-Id: <1478206203-4606-2-git-send-email-rth@twiddle.net>
-
由 Peter Maydell 提交于
target-arm queue: * add VBAR support to ARM1176 CPUs * hw/i2c: add NULL check to i2c slave init callbacks * pxa2xx.c: fix trailing whitespace * aspeed: various cleanups * aspeed: add romulus-bmc board * virt: add 2.9 machine type * gicv3: don't signal Pending+Active interrupts to CPU * gicv3: fix incorrect usage of fieldoffset * arm: log AArch64 exception returns * gicv3: fix aff3 field in typer register * aarch64: fix ldst_single_struct on BE hosts * aarch64: fix vec_reg_offset on BE hosts * arm: fix Cortex-A8 MVFR1 register value * cadence_uart: check if receiver timeout counter disabled * cadence_uart: check register values on migration # gpg: Signature made Tue 27 Dec 2016 15:19:26 GMT # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20161227: (25 commits) target-arm: Add VBAR support to ARM1176 CPUs hw/i2c: Add a NULL check for i2c slave init callbacks hw/arm: remove trailing whitespace aspeed/smc: set the number of flash modules for the FMC controller aspeed/smc: improve segment register support aspeed/scu: fix SCU region size aspeed: change SoC revision of the palmetto-bmc machine aspeed: add the definitions for the AST2400 A1 SoC aspeed: add a memory region for SRAM aspeed: add support for the romulus-bmc board aspeed: extend the board configuration with flash models aspeed: attach the second SPI controller object to the SoC aspeed: remove cannot_destroy_with_object_finalize_yet aspeed: QOMify the CPU object and attach it to the SoC m25p80: add support for the mx66l1g45g hw/arm/virt: add 2.9 machine type hw/intc/arm_gicv3: Don't signal Pending+Active interrupts to CPU hw/intc/arm_gicv3: Remove incorrect usage of fieldoffset target-arm: Log AArch64 exception returns hw/intc/arm_gicv3_common: fix aff3 in typer ... Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
- 27 12月, 2016 17 次提交
-
-
由 Cédric Le Goater 提交于
ARM1176 CPUs have TrustZone support and can use the Vector Base Address Register, but currently, qemu only adds VBAR support to ARMv7 CPUs. Fix this by adding a new feature ARM_FEATURE_VBAR which can used for ARMv7 and ARM1176 CPUs. The VBAR feature is always set for ARMv7 because some legacy boards require it even if this is not architecturally correct. Signed-off-by: NCédric Le Goater <clg@kaod.org> Message-id: 1481810970-9692-1-git-send-email-clg@kaod.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Alastair D'Silva 提交于
Add a NULL check for i2c slave init callbacks, so that we no longer need to implement empty init functions. Signed-off-by: NAlastair D'Silva <alastair@d-silva.org> Message-id: 20161202054617.6749-4-alastair@au1.ibm.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> [PMM: squashed in later tweak from Alistair to if() phrasing] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Alastair D'Silva 提交于
Remove trailing whitespace in hw/arm/pxa2xx.c Signed-off-by: NAlastair D'Silva <alastair@d-silva.org> Message-id: 20161202054617.6749-3-alastair@au1.ibm.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Cédric Le Goater 提交于
Add a new configuration field at the board level and propagate the value using the "num-cs" property of the FMC controller model. Signed-off-by: NCédric Le Goater <clg@kaod.org> Message-id: 1480434248-27138-14-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Cédric Le Goater 提交于
The HW does not enforce all the rules in the specs and allows a few "curious" setups like zero size segments and overlaps. So change the model to be in sync but keep the warnings which are always interesting for debug. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NJoel Stanley <joel@jms.id.au> Message-id: 1480434248-27138-13-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Cédric Le Goater 提交于
Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NJoel Stanley <joel@jms.id.au> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-12-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Cédric Le Goater 提交于
The palmetto BMC machine uses a AST2400 revision A1 SoC. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NJoel Stanley <joel@jms.id.au> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-11-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Cédric Le Goater 提交于
There is not much differences with the A0 revision apart from the DDR calibration. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NJoel Stanley <joel@jms.id.au> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-10-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Cédric Le Goater 提交于
The size of the SRAM depends on the SoC model, so use a per-soc definition when creating the region. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NJoel Stanley <joel@jms.id.au> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-9-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Cédric Le Goater 提交于
The Romulus machine is an OpenPOWER system with an AST2500 SoC for the BMC and a POWER9 chip for the host. It does not make much difference for qemu a part from the fact that the FMC controller has two SPI flash module. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NJoel Stanley <joel@jms.id.au> Message-id: 1480434248-27138-8-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Cédric Le Goater 提交于
Future machine will use different flash models for the FMC and the SPI controllers. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NJoel Stanley <joel@jms.id.au> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-7-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Cédric Le Goater 提交于
Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-6-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Cédric Le Goater 提交于
With commit ce5b1bbf ("exec: move cpu_exec_init() calls to realize functions"), we can now remove cannot_destroy_with_object_finalize_yet. Suggested-by: NAndrew Jeffery <andrew@aj.id.au> Signed-off-by: NCédric Le Goater <clg@kaod.org> Message-id: 1480434248-27138-5-git-send-email-clg@kaod.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Cédric Le Goater 提交于
Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NJoel Stanley <joel@jms.id.au> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-4-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Cédric Le Goater 提交于
Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NMarcin Krzeminski <marcin.krzeminski@nokia.com> Reviewed-by: NJoel Stanley <joel@jms.id.au> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-3-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Peter Maydell 提交于
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAndrew Jones <drjones@redhat.com>
-
由 Peter Maydell 提交于
The GICv3 requires that we only signal Pending interrupts to the CPU. This category does not include Pending+Active interrupts, which means we need to check whether the interrupt is Active in the gicr_int_pending() and gicd_int_pending() functions. Interrupts are rarely in the Active+Pending state, but KVM uses this as part of its handling of the virtual timer, so this bug was causing KVM to go into an infinite loop of taking the vtimer interrupt when the guest first triggered it. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com>
-