- 19 8月, 2015 3 次提交
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由 Richard Henderson 提交于
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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由 Richard Henderson 提交于
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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由 Richard Henderson 提交于
This avoids having to manually swap them around when swapping to and from PALmode. We simply encode the shadow registers into the translation. The VMStateDescription version changes, because the meaning of "shadow" changes in the save file when in PALmode. It would be possible to fix this, but I don't think it's worth the effort. Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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- 14 8月, 2015 5 次提交
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由 Peter Maydell 提交于
# gpg: Signature made Fri 14 Aug 2015 14:54:27 BST using RSA key ID C0DE3057 # gpg: Good signature from "Jeffrey Cody <jcody@redhat.com>" # gpg: aka "Jeffrey Cody <jeff@codyprime.org>" # gpg: aka "Jeffrey Cody <codyprime@gmail.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 9957 4B4D 3474 90E7 9D98 D624 BDBE 7B27 C0DE 3057 * remotes/cody/tags/block-pull-request: mirror: Fix coroutine reentrance block/mirror: limit qiov to IOV_MAX elements Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
# gpg: Signature made Fri 14 Aug 2015 15:41:14 BST using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" * remotes/stefanha/tags/block-pull-request: throttle: add throttle_max_is_missing_limit() test throttle: refuse bps_max/iops_max without bps/iops Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Kevin Wolf 提交于
This fixes a regression introduced by commit dcfb3beb ("mirror: Do zero write on target if sectors not allocated"), which was reported to cause aborts with the message "Co-routine re-entered recursively". The cause for this bug is the following code in mirror_iteration_done(): if (s->common.busy) { qemu_coroutine_enter(s->common.co, NULL); } This has always been ugly because - unlike most places that reenter - it doesn't have a specific yield that it pairs with, but is more uncontrolled. What we really mean here is "reenter the coroutine if it's in one of the four explicit yields in mirror.c". This used to be equivalent with s->common.busy because neither mirror_run() nor mirror_iteration() call any function that could yield. However since commit dcfb3beb this doesn't hold true any more: bdrv_get_block_status_above() can yield. So what happens is that bdrv_get_block_status_above() wants to take a lock that is already held, so it adds itself to the queue of waiting coroutines and yields. Instead of being woken up by the unlock function, however, it gets woken up by mirror_iteration_done(), which is obviously wrong. In most cases the code actually happens to cope fairly well with such cases, but in this specific case, the unlock must already have scheduled the coroutine for wakeup when mirror_iteration_done() reentered it. And then the coroutine happened to process the scheduled restarts and tried to reenter itself recursively. This patch fixes the problem by pairing the reenter in mirror_iteration_done() with specific yields instead of abusing s->common.busy. Cc: qemu-stable@nongnu.org Signed-off-by: NKevin Wolf <kwolf@redhat.com> Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com> Reviewed-by: NStefan Hajnoczi <stefanha@redhat.com> Reviewed-by: NJeff Cody <jcody@redhat.com> Message-id: 1439455310-11263-1-git-send-email-kwolf@redhat.com Signed-off-by: NJeff Cody <jcody@redhat.com>
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由 Jeff Cody 提交于
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由 Peter Maydell 提交于
MIPS patches 2015-08-13 Changes: * mips32r5-generic CPU updated and renamed to P5600 * improvements in LWL/LDL, logging and fulong2e # gpg: Signature made Thu 13 Aug 2015 17:10:59 BST using RSA key ID 0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4 4FC0 5211 8E3C 0B29 DA6B * remotes/lalrae/tags/mips-20150813: target-mips: Use CPU_LOG_INT for logging related to interrupts hw/pci-host/bonito: Avoid buffer overrun for bad LDMA/COP accesses target-mips: simplify LWL/LDL mask generation target-mips: update mips32r5-generic into P5600 Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 13 8月, 2015 32 次提交
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由 Richard Henderson 提交于
There are now no unconditional uses of qemu_log in the subdirectory. Signed-off-by: NRichard Henderson <rth@twiddle.net> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Peter Maydell 提交于
The LDMA and COP memory regions represent four 32 bit registers each, but the memory regions themselves are 0x100 bytes large. Add guards to the read and write accessors so that bogus accesses beyond the four defined registers don't just run off the end of the bonldma and boncop structs and into whatever lies beyond. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Aurelien Jarno 提交于
The LWL/LDL instructions mask the GPR with a mask depending on the address alignement. It is currently computed by doing: mask = 0x7fffffffffffffffull >> (t1 ^ 63) It's simpler to generate it by doing: mask = ~(-1 << t1) It uses one TCG instruction less, and it avoids a 32/64-bit constant loading which can take a few instructions on RISC hosts. Cc: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> Reviewed-by: NRichard Henderson <rth@twiddle.net> Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Yongbok Kim 提交于
As full specification of P5600 is available, mips32r5-generic should be renamed to P5600 and corrected as its intention. Correct PRid and detail of configuration. Features which are not currently supported are described as FIXME. Fix Config.MM bit location Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com> [leon.alrae@imgtec.com: correct cache line sizes and LLAddr shift] Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Peter Maydell 提交于
virtio,pc,acpi fixes, cleanups Mostly cleanups, notably Eduardo's compat code rework, and smbios rearrangement for use by ARM. Signed-off-by: NMichael S. Tsirkin <mst@redhat.com> # gpg: Signature made Thu 13 Aug 2015 12:59:16 BST using RSA key ID D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" * remotes/mst/tags/for_upstream: (24 commits) MAINTAINERS: list smbios maintainers smbios: move smbios code into a common folder smbios: remove dependency on x86 e820 tables smbios: extract x86 smbios building code into a function acpi: avoid potential uninitialized access to cpu_hp_io_base virtio-net: remove useless codes pci: allow 0 address for PCI IO/MEM regions pc: Remove redundant arguments from pc_memory_init() pc: Remove redundant arguments from pc_cmos_init() pc: Remove redundant arguments from *load_linux() pc: Use PCMachineState as pc_guest_info_init() argument pc: Move {above,below}_4g_mem_size variables to PCMachineState pc: Use PCMachineState for pc_memory_init() argument pc: Use PCMachineState for pc_cmos_init() argument pc: Eliminate pc_default_machine_options() pc: Eliminate pc_common_machine_options() pc: Move PCMachineClass, PCMachineState to qemu/typedefs.h pc: Rename pc_machine variables to pcms pc: Use error_abort when registering properties target-i386: Remove x86_cpu_compat_set_features() ... Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Michael S. Tsirkin 提交于
Now that smbios has its own directory, list its maintainers. Same people as ACPI so just reuse that entry. Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Wei Huang 提交于
To share smbios among different architectures, this patch moves SMBIOS code (smbios.c and smbios.h) from x86 specific folders into new hw/smbios directories. As a result, CONFIG_SMBIOS=y is defined in x86 default config files. Acked-by: NGabriel Somlo <somlo@cmu.edu> Tested-by: NGabriel Somlo <somlo@cmu.edu> Reviewed-by: NLaszlo Ersek <lersek@redhat.com> Tested-by: NLeif Lindholm <leif.lindholm@linaro.org> Signed-off-by: NWei Huang <wei@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Wei Huang 提交于
Current smbios builds type 19 table from e820, which is x86 specific. This patch removes smbios' dependency on e820 by passing an array of memory area to smbios_get_tables(). Acked-by: NGabriel Somlo <somlo@cmu.edu> Tested-by: NGabriel Somlo <somlo@cmu.edu> Reviewed-by: NLaszlo Ersek <lersek@redhat.com> Tested-by: NLeif Lindholm <leif.lindholm@linaro.org> Signed-off-by: NWei Huang <wei@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Wei Huang 提交于
This patch extracts out the procedure of buidling x86 SMBIOS tables into a dedicated function. Acked-by: NGabriel Somlo <somlo@cmu.edu> Tested-by: NGabriel Somlo <somlo@cmu.edu> Reviewed-by: NLaszlo Ersek <lersek@redhat.com> Tested-by: NLeif Lindholm <leif.lindholm@linaro.org> Signed-off-by: NWei Huang <wei@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Daniel P. Berrange 提交于
When building QEMU with Mingw64 toolchain I see a warning CC x86_64-softmmu/hw/i386/acpi-build.o hw/i386/acpi-build.c: In function 'acpi_build': hw/i386/acpi-build.c:1138:9: warning: 'pm.cpu_hp_io_base' may be used uninitialized in this function [-Wmaybe-uninitialized] aml_append(crs, ^ hw/i386/acpi-build.c:1666:16: note: 'pm.cpu_hp_io_base' was declared here AcpiPmInfo pm; ^ In acpi_get_pm_info() some of the fields are pre-initialized to 0, but this one was missed. Signed-off-by: NDaniel P. Berrange <berrange@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com> Reviewed-by: NIgor Mammedov <imammedo@redhat.com>
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由 Jason Wang 提交于
After commit 40bad8f3("virtio-net: fix used len for tx"), async_tx.len was no longer used afterwards. So remove useless codes with it. Signed-off-by: NJason Wang <jasowang@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Laurent Vivier 提交于
Some kernels program a 0 address for io regions. PCI 3.0 spec section 6.2.5.1 doesn't seem to disallow this. based on patch by Michael Roth <mdroth@linux.vnet.ibm.com> Add pci_allow_0_addr in MachineClass to conditionally allow addr 0 for pseries, as this can break other architectures. This patch allows to hotplug PCI card in pseries machine, as the first added card BAR0 is always set to 0 address. This as a temporary hack, waiting to fix PCI memory priorities for more machine types... Signed-off-by: NLaurent Vivier <lvivier@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Eduardo Habkost 提交于
Remove arguments that can be found in PCMachineState. Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Eduardo Habkost 提交于
Remove arguments that can be found in PCMachineState. Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Eduardo Habkost 提交于
Remove arguments that can be found in PCMachineState. Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Eduardo Habkost 提交于
Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Eduardo Habkost 提交于
This will make the info readily available for the other initialization functions, and will allow us to simplify their argument list. Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Eduardo Habkost 提交于
pc_memory_init() already expects a PCMachineState object, there's no point in upcasting it to MachineState before calling the function. Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Eduardo Habkost 提交于
pc_cmos_init() already expects a PCMachineState object, there's no point in upcasting it to MachineState before calling the function. While doing it, reorder the arguments so PCMachineState is the first function argument. Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Eduardo Habkost 提交于
The only PC machines that didn't call pc_default_machine_options() were isaps and xenfv. Both were already overwriting max_cpus, and only isapc was not overwriting hot_add_cpu. After making isapc set hot_add_cpu to NULL, we can move the pc_default_machine_options() code the PC common class_init. Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Eduardo Habkost 提交于
All TYPE_PC_MACHINE subclasses call pc_common_machine_options(). TYPE_PC_MACHINE can simply initialize the common options on class_init directly. Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Eduardo Habkost 提交于
They will be used inside hw/xen/xen.h, which doesn't include hw/i386/pc.h. Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Eduardo Habkost 提交于
Make the code use the same variable name everywhere. "pcms" is already being used in existing code and it's shorter. Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Eduardo Habkost 提交于
No errors should happen when registering the properties, but we shouldn't silently ignore them if they happen. Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Eduardo Habkost 提交于
The function is not used by PC code anymore and can be removed. Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Eduardo Habkost 提交于
Now we can use compat_props to keep CPUID feature compatibility, using the boolean QOM properties for CPUID feature flags. This simplifies the compatibility code, and reduces duplication between pc_piix.c and pc_q35.c. Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Eduardo Habkost 提交于
The existing i440fx initialization code sets a PCI config register that isn't documented anywhere in the Intel 440FX datasheet. Register 0x57 is DRAMC (DRAM Control) and has nothing to do with the RAM size. This was implemented in commit ec5f92ce because old coreboot code tried to read registers 0x5a-0x5f,0x56,0x57 to get the RAM size from QEMU, but I couldn't find out why coreboot did that. I assume it was a mistake, and the original code was supposed to be reading the DRB[0-7] registers (offsets 0x60-0x67). Document that coreboot-specific register offset in a macro and a comment, for future reference. Cc: Ed Swierk <eswierk@skyportsystems.com> Cc: Richard Smith <smithbone@gmail.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Victor Kaplansky 提交于
The old rules.mak loads dependency .d files using include directive with file glob pattern "*.d". This breaks the build when build tree has left-over *.d files from another build. This patch fixes this by - loading precise list of .d files made from *.o and *.mo. - specifying explicit list of required dependency info files for *.hex autogenerated sources. Note that Makefile still includes some .d in root directory by including "*.d". Signed-off-by: NVictor Kaplansky <victork@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Victor Kaplansky 提交于
In rules like "bar/%.o: %.c" there is a difference between $(*D) and $(@D). $(*D) expands to '.', while $(@D) expands to 'bar'. It is cleaner to generate *.d in the same directory where appropriate *.o resides. This allows precise including of dependency info from .d files. As a hack, we also touch two sources for generated *.hex files. Without this hack, anyone doing "git pull; make" will not get *.hex rebuilt correctly since the dependency file would be missing. Signed-off-by: NVictor Kaplansky <victork@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Peter Maydell 提交于
target-arm queue: * i.MX code cleanup/refactorings * i.MX UART fix to work with uninitialized chardev * minor GIC code refactorings * implement the ARM Secure physical timer * implement the ARM Hypervisor timer # gpg: Signature made Thu 13 Aug 2015 11:40:56 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20150813: (27 commits) i.MX: Fix UART driver to work with unitialized "chardev" device hw/cpu/a15mpcore: Wire up hyp and secure physical timer interrupts hw/arm/virt: Wire up secure timer interrupt target-arm: Add AArch32 banked register access to secure physical timer target-arm: Add the AArch64 view of the Secure physical timer target-arm: Add debug check for mismatched cpreg resets Introduce gic_class_name() instead of repeating condition hw/arm/gic: Kill code duplication Merge memory_region_init_reservation() into memory_region_init_io() i.MX: Fix Coding style for GPT emulator i.MX: Split GPT emulator in a header file and a source file i.MX: Fix Coding style for EPIT emulator i.MX: Split EPIT emulator in a header file and a source file i.MX: Fix Coding style for CCM emulator i.MX: Split CCM emulator in a header file and a source file i.MX: Fix Coding style for AVIC emulator. i.MX: Split AVIC emulator in a header file and a source file i.MX:Fix Coding style for UART emulator. i.MX: Move serial initialization to init/realize of DeviceClass. i.MX: Split UART emulator in a header file and a source file ... Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Jean-Christophe Dubois 提交于
The "chardev" property initialization might have failed (for example because there are not enough chardevs provided by QEMU). The serial device emulator needs to be able to work with an uninitialized (NULL) chardev device pointer. This patch adds some missing tests on the chr pointer value before using it. Signed-off-by: NJean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1438342461-18967-1-git-send-email-jcd@tribudubois.net Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Since we now support both the hypervisor and the secure physical timer, wire their interrupt lines up in the a15mpcore wrapper object. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1437047249-2357-5-git-send-email-peter.maydell@linaro.org Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com>
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