1. 17 12月, 2018 2 次提交
  2. 16 6月, 2018 1 次提交
    • R
      tcg: Reduce max TB opcode count · 9f754620
      Richard Henderson 提交于
      Also, assert that we don't overflow any of two different offsets into
      the TB. Both unwind and goto_tb both record a uint16_t for later use.
      
      This fixes an arm-softmmu test case utilizing NEON in which there is
      a TB generated that runs to 7800 opcodes, and compiles to 96k on an
      x86_64 host.  This overflows the 16-bit offset in which we record the
      goto_tb reset offset.  Because of that overflow, we install a jump
      destination that goes to neverland.  Boom.
      
      With this reduced op count, the same TB compiles to about 48k for
      aarch64, ppc64le, and x86_64 hosts, and neither assertion fires.
      
      Cc: qemu-stable@nongnu.org
      Reported-by: N"Jason A. Donenfeld" <Jason@zx2c4.com>
      Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
      Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
      9f754620
  3. 03 11月, 2017 1 次提交
  4. 17 9月, 2017 2 次提交
  5. 08 9月, 2017 8 次提交
  6. 06 9月, 2017 8 次提交
  7. 06 6月, 2017 1 次提交
  8. 14 1月, 2017 1 次提交
  9. 11 1月, 2017 6 次提交
  10. 24 12月, 2016 2 次提交
  11. 16 9月, 2016 2 次提交
  12. 06 7月, 2016 2 次提交
    • S
      tcg: Improve the alignment check infrastructure · 1f00b27f
      Sergey Sorokin 提交于
      Some architectures (e.g. ARMv8) need the address which is aligned
      to a size more than the size of the memory access.
      To support such check it's enough the current costless alignment
      check implementation in QEMU, but we need to support
      an alignment size specifying.
      Signed-off-by: NSergey Sorokin <afarallax@yandex.ru>
      Message-Id: <1466705806-679898-1-git-send-email-afarallax@yandex.ru>
      Signed-off-by: NRichard Henderson <rth@twiddle.net>
      [rth: Assert in tcg_canonicalize_memop.  Leave get_alignment_bits
      available for, though unused by, user-mode.  Retain logging difference
      based on ALIGNED_ONLY.]
      1f00b27f
    • R
      tcg: Optimize spills of constants · 59d7c14e
      Richard Henderson 提交于
      While we can store constants via constrants on INDEX_op_st_i32 et al,
      we weren't able to spill constants to backing store.
      
      Add a new backend interface, tcg_out_sti, which may store the constant
      (and is allowed to fail).  Rearrange the temp_* helpers so that we only
      attempt to directly store a constant when the temp is becoming dead/free.
      Signed-off-by: NRichard Henderson <rth@twiddle.net>
      59d7c14e
  13. 13 5月, 2016 2 次提交
  14. 21 4月, 2016 2 次提交
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