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  1. 24 2月, 2013 1 次提交
    • P
      Replace all setjmp()/longjmp() with sigsetjmp()/siglongjmp() · 6ab7e546
      由 Peter Maydell 提交于 
      The setjmp() function doesn't specify whether signal masks are saved and
restored; on Linux they are not, but on BSD (including MacOSX) they are.
We want to have consistent behaviour across platforms, so we should
always use "don't save/restore signal mask" (this is also generally
going to be faster). This also works around a bug in MacOSX where the
signal-restoration on longjmp() affects the signal mask for a completely
different thread, not just the mask for the thread which did the longjmp.
The most visible effect of this was that ctrl-C was ignored on MacOSX
because the CPU thread did a longjmp which resulted in its signal mask
being applied to every thread, so that all threads had SIGINT and SIGTERM
blocked.

The POSIX-sanctioned portable way to do a jump without affecting signal
masks is to siglongjmp() to a sigjmp_buf which was created by calling
sigsetjmp() with a zero savemask parameter, so change all uses of
setjmp()/longjmp() accordingly. [Technically POSIX allows sigsetjmp(buf, 0)
to save the signal mask; however the following siglongjmp() must not
restore the signal mask, so the pair can be effectively considered as
"sigjmp/longjmp which don't touch the mask".]

For Windows we provide a trivial sigsetjmp/siglongjmp in terms of
setjmp/longjmp -- this is OK because no user will ever pass a non-zero
savemask.

The setjmp() uses in tests/tcg/test-i386.c and tests/tcg/linux-test.c
are left untouched because these are self-contained singlethreaded
test programs intended to be run under QEMU's Linux emulation, so they
have neither the portability nor the multithreading issues to deal with.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Tested-by: NStefan Weil <sw@weilnetz.de>
Reviewed-by: NLaszlo Ersek <lersek@redhat.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
      6ab7e546
  3. 16 2月, 2013 3 次提交
  5. 19 12月, 2012 3 次提交
  7. 31 10月, 2012 1 次提交
  9. 05 10月, 2012 1 次提交
  11. 27 8月, 2012 1 次提交
  13. 24 8月, 2012 1 次提交
  15. 11 8月, 2012 1 次提交
  17. 28 7月, 2012 2 次提交
  19. 10 7月, 2012 1 次提交
    • J
      apic: Defer interrupt updates to VCPU thread · 5d62c43a
      由 Jan Kiszka 提交于 
      KVM performs TPR raising asynchronously to QEMU, specifically outside
QEMU's global lock. When an interrupt is injected into the APIC and TPR
is checked to decide if this can be delivered, a stale TPR value may be
used, causing spurious interrupts in the end.

Fix this by deferring apic_update_irq to the context of the target VCPU.
We introduce a new interrupt flag for this, CPU_INTERRUPT_POLL. When it
is set, the VCPU calls apic_poll_irq before checking for further pending
interrupts. To avoid special-casing KVM, we also implement this logic
for TCG mode.
Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: NAvi Kivity <avi@redhat.com>
      5d62c43a
  21. 29 6月, 2012 1 次提交
    • B
      x86: avoid AREG0 for exceptions · 77b2bc2c
      由 Blue Swirl 提交于 
      Add an explicit CPUX86State parameter instead of relying on AREG0.

Merge raise_exception_env() to raise_exception(), likewise with
raise_exception_err_env() and raise_exception_err().

Introduce cpu_svm_check_intercept_param() and cpu_vmexit()
as wrappers.
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
      77b2bc2c
  23. 25 6月, 2012 1 次提交
  25. 15 6月, 2012 1 次提交
  27. 05 6月, 2012 2 次提交
  29. 16 4月, 2012 1 次提交
  31. 30 3月, 2012 1 次提交
    • A
      qtest: add test framework · c7f0f3b1
      由 Anthony Liguori 提交于 
      The idea behind qtest is pretty simple.  Instead of executing a CPU via TCG or
KVM, rely on an external process to send events to the device model that the CPU
would normally generate.

qtest presents itself as an accelerator.  In addition, a new option is added to
establish a qtest server (-qtest) that takes a character device.  This is what
allows the external process to send CPU events to the device model.

qtest uses a simple line based protocol to send the events.  Documentation of
that protocol is in qtest.c.

I considered reusing the monitor for this job.  Adding interrupts would be a bit
difficult.  In addition, logging would also be difficult.

qtest has extensive logging support.  All protocol commands are logged with
time stamps using a new command line option (-qtest-log).  Logging is important
since ultimately, this is a feature for debugging.
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
      c7f0f3b1
  33. 17 3月, 2012 1 次提交
    • S
      w64: Fix data type of next_tb and tcg_qemu_tb_exec · 69784eae
      由 Stefan Weil 提交于 
      next_tb is the numeric value of a tcg target (= QEMU host) address.

Using tcg_target_ulong instead of unsigned long shows this and makes
the code portable for hosts with an unusual size of long (w64).

The type cast '(long)(next_tb & ~3)' was not needed (casting
unsigned long to long does not change the bits, and nor does
casting long to pointer for most (= all non w64) hosts.
It is removed here.

Macro or function tcg_qemu_tb_exec is used to set next_tb.
The function also returns next_tb. Therefore tcg_qemu_tb_exec
must return a tcg_target_ulong.
Signed-off-by: NStefan Weil <sw@weilnetz.de>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
      69784eae
  35. 15 3月, 2012 3 次提交
  37. 10 2月, 2012 1 次提交
  39. 06 10月, 2011 1 次提交
    • E
      PPC: Fix sync instructions problem in SMP · 4e85f82c
      由 Elie Richa 提交于 
      In the current emulation of the load-and-reserve (lwarx) and
store-conditional (stwcx.) instructions, the internal reservation
mechanism is taken into account, however each CPU has its own
reservation information and this information is not synchronized between
CPUs to perform proper synchronization.
The following test case with 2 CPUs shows that the semantics of the
"lwarx" and "stwcx." instructions are not preserved by the emulation.
The test case does the following :
	- CPU0: reserve a memory location
	- CPU1: reserve the same memory location
	- CPU0: perform stwcx. on the location
The last store-conditional operation succeeds while it is supposed to
fail since the reservation was supposed to be lost at the second reserve
operation.

This (one line) patch fixes this problem in a very simple manner by
removing the reservation of a CPU every time it is scheduled (in
cpu_exec()). While this is a harsh workaround, it does not affect the
guest code much because reservations are usually held for a very short
time, that is an lwarx is almost always followed by an stwcx. a few
instructions below. Therefore, in most cases, the reservation will be
taken and consumed before a CPU switch occurs. However in the rare case
where a CPU switch does occur between the lwarx and its corresponding
stwcx.  this patch solves a potential erroneous behavior of the
synchronization instructions.
Signed-off-by: NElie Richa <richa@adacore.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>
      4e85f82c
  41. 11 9月, 2011 2 次提交
  43. 10 9月, 2011 1 次提交
  45. 13 7月, 2011 1 次提交
  47. 27 6月, 2011 6 次提交
  49. 21 6月, 2011 1 次提交
  51. 01 6月, 2011 1 次提交