1. 02 11月, 2014 1 次提交
    • M
      virtio-pci: fix migration for pci bus master · 68a27b20
      Michael S. Tsirkin 提交于
      Current support for bus master (clearing OK bit) together with the need to
      support guests which do not enable PCI bus mastering, leads to extra state in
      VIRTIO_PCI_FLAG_BUS_MASTER_BUG bit, which isn't robust in case of cross-version
      migration for the case when guests use the device before setting DRIVER_OK.
      
      Rip out this code, and replace it:
      -   Modern QEMU doesn't need VIRTIO_PCI_FLAG_BUS_MASTER_BUG
          so just drop it for latest machine type.
      -   For compat machine types, set PCI_COMMAND if DRIVER_OK
          is set.
      
      As this is needed for 2.1 for both pc and ppc, move PC_COMPAT macros from pc.h
      to a new common header.
      
      Cc: Greg Kurz <gkurz@linux.vnet.ibm.com>
      Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
      Reviewed-by: NAlexander Graf <agraf@suse.de>
      
      68a27b20
  2. 20 10月, 2014 2 次提交
  3. 20 9月, 2014 1 次提交
  4. 08 9月, 2014 13 次提交
  5. 25 8月, 2014 1 次提交
  6. 15 7月, 2014 2 次提交
    • A
      spapr: Enable use of huge pages · f92f5da1
      Alexey Kardashevskiy 提交于
      0b183fc8 "memory: move mem_path handling to
      memory_region_allocate_system_memory" disabled -mempath use for all
      machines that do not use memory_region_allocate_system_memory() to
      register RAM. Since SPAPR uses memory_region_init_ram(), the huge pages
      support was disabled for it.
      
      This replaces memory_region_init_ram()+vmstate_register_ram_global() with
      memory_region_allocate_system_memory() to get huge pages back.
      
      This changes RAM size from (ram_limit - rma_alloc_size) to ram_limit as
      the previous patch moved RMA memory region allocation after RAM allocation
      and therefore this change does not have immediate effect but simplifies
      the code.
      Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      f92f5da1
    • A
      spapr: Move RMA memory region registration code · 658fa66b
      Alexey Kardashevskiy 提交于
      PPC970 does not support VRMA (virtual RMA) so real memory required
      for SLOF to execute must be allocated by the KVM_ALLOCATE_RMA ioctl.
      Later this memory is used as a part of the guest RAM area.
      The RMA allocating code also registers a memory region for this piece
      of RAM.
      
      We are going to simplify memory regions layout: RMA memory region
      will be a subregion in the RAM memory region, both starting from zero.
      This way we will not have to take care of start address alignment for
      the piece of RAM next to the RMA.
      
      This moves memory region business closer to the RAM memory region
      creation/allocation code.
      
      As this is a mechanical patch, no change in behaviour is expected.
      Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru>
      [agraf: fix compilation on non-kvm systems]
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      658fa66b
  7. 08 7月, 2014 1 次提交
  8. 27 6月, 2014 5 次提交
  9. 19 6月, 2014 1 次提交
  10. 16 6月, 2014 13 次提交
    • B
      spapr_pci: Advertise MSI quota · 9dbae977
      Badari Pulavarty 提交于
      Hotplug of multiple disks fails due to MSI vector quota check.
      Number of MSI vectors default to 8 allowing only 4 devices.
      This happens on RHEL6.5 guest. RHEL7 and SLES11 guests fallback
      to INTX.
      
      One way to workaround the issue is to increase total MSIs,
      so that MSI quota check allows us to hotplug multiple disks.
      
      This sets the quota to the maximum number of interupts XICS has
      which is 1024 now (XICS_IRQS). This moves XICS_IRQS from spapr.c
      to xics.h for wider visibility.
      Signed-off-by: NBadari Pulavarty <pbadari@us.ibm.com>
      [aik: put XICS_IRQS=1024 instead of 64i, fixed endianness and size]
      Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      9dbae977
    • E
      spapr: Add kvm-type property · 23825581
      Eduardo Habkost 提交于
      The kvm-type machine option was left out when MachineState was
      introduced, preventing the kvm-type option from being used. Add the
      missing property to the sPAPR machine class, so it can be used.
      Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
      Tested-by: NAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      23825581
    • E
    • A
      PPC: spapr: Expose /hypervisor node in device tree · f7d69146
      Alexander Graf 提交于
      PR KVM supports an ePAPR compliant hypercall interface in parallel to the
      normal sPAPR one. Expose the ePAPR /hypervisor node and properties to the
      guest so it can use it.
      
      This enables magic page sharing on PR KVM with -M pseries.
      
      However we had a few nasty bugs in the magic page implementation on vcpus
      newer than 970 (p7, p8) that KVM now has workarounds for. It indicates that
      it does have these workarounds through the PPC_FIXUP_HCALL capability.
      
      To not expose broken guest kernels to issues on host kernels that don't
      have the fixups in place, we don't expose working hypercall instructions
      when the fixups are not available so that the guest can never active the
      magic page.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      f7d69146
    • A
      spapr_iommu: Enable multiple TCE requests · da95324e
      Alexey Kardashevskiy 提交于
      Currently only single TCE entry per request is supported (H_PUT_TCE).
      However PAPR+ specification allows multiple entry requests such as
      H_PUT_TCE_INDIRECT and H_STUFF_TCE. Having less transitions to the host
      kernel via ioctls, support of these calls can accelerate IOMMU operations.
      
      This implements H_STUFF_TCE and H_PUT_TCE_INDIRECT.
      
      This advertises "multi-tce" capability to the guest if the host kernel
      supports it (KVM_CAP_SPAPR_MULTITCE) or guest is running in TCG mode.
      Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      da95324e
    • A
      spapr: Enable dynamic change of the supported hypercalls list · a1d59c0f
      Alexey Kardashevskiy 提交于
      At the moment the "ibm,hypertas-functions" list is fixed. However some
      calls should be listed there if they are supported by QEMU or the host
      kernel.
      
      This enables hyperrtas_prop to grow on stack by adding
      a SPAPR_HYPERRTAS_ADD macro. "qemu,hypertas-functions" is converted as well.
      
      The first user of this is going to be a "multi-tce" property.
      Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      a1d59c0f
    • A
      spapr: Implement processor compatibility in ibm, client-architecture-support · 3794d548
      Alexey Kardashevskiy 提交于
      Modern Linux kernels support last POWERPC CPUs so when a kernel boots,
      in most cases it can find a matching cpu_spec in the kernel's cpu_specs
      list. However if the kernel is quite old, it may be missing a definition
      of the actual CPU. To provide an ability for old kernels to work on modern
      hardware, a Processor Compatibility Mode has been introduced
      by the PowerISA specification.
      
      >From the hardware prospective, it is supported by the Processor
      Compatibility Register (PCR) which is defined in PowerISA. The register
      enables one of the compatibility modes (2.05/2.06/2.07).
      Since PCR is a hypervisor privileged register and cannot be
      directly accessed from the guest, the mode selection is done via
      ibm,client-architecture-support (CAS) RTAS call using which the guest
      specifies what "raw" and "architected" CPU versions it supports.
      QEMU works out the best match, changes a "cpu-version" property of
      every CPU and notifies the guest about the change by setting these
      properties in the buffer passed as a response on a custom H_CAS hypercall.
      
      This implements ibm,client-architecture-support parameters parsing
      (now only for PVRs) and cooks the device tree diff with new values for
      "cpu-version", "ibm,ppc-interrupt-server#s" and
      "ibm,ppc-interrupt-server#s" properties.
      Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      3794d548
    • A
      spapr: Limit threads per core according to current compatibility mode · 2a48d993
      Alexey Kardashevskiy 提交于
      This puts a limit to the number of threads per core based on the current
      compatibility mode. Although PowerISA specs do not specify the maximum
      threads per core number, the linux guest still expects that
      PowerISA2.05-compatible CPU supports only 2 threads per core as this
      is what POWER6 (2.05 compliant CPU) implements, the same is for
      POWER7 (2.06, 4 threads) and POWER8 (2.07, 8 threads).
      
      This calls spapr_fixup_cpu_smt_dt() with the maximum allowed number of
      threads which affects ibm,ppc-interrupt-server#s and
      ibm,ppc-interrupt-gserver#s properties.
      
      The number of CPU nodesremains unchanged.
      Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      2a48d993
    • A
      spapr: Rework spapr_fixup_cpu_dt() · 82677ed2
      Alexey Kardashevskiy 提交于
      In PPC code we usually use the "cs" name for a CPUState* variables
      and "cpu" for PowerPCCPU. So let's change spapr_fixup_cpu_dt() to
      use same rules as spapr_create_fdt_skel() does.
      
      This adds missing nodes creation if they do not already exist in
      the current device tree, this is going to be used from
      the client-architecture-support handler.
      Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      82677ed2
    • A
      spapr: Add ibm, client-architecture-support call · 2a6593cb
      Alexey Kardashevskiy 提交于
      The PAPR+ specification defines a ibm,client-architecture-support (CAS)
      RTAS call which purpose is to provide a negotiation mechanism for
      the guest and the hypervisor to work out the best compatibility parameters.
      During the negotiation process, the guest provides an array of various
      options and capabilities which it supports, the hypervisor adjusts
      the device tree and (optionally) reboots the guest.
      
      At the moment the Linux guest calls CAS method at early boot so SLOF
      gets called. SLOF allocates a memory buffer for the device tree changes
      and calls a custom KVMPPC_H_CAS hypercall. QEMU parses the options,
      composes a diff for the device tree, copies it to the buffer provided
      by SLOF and returns to SLOF. SLOF updates the device tree and returns
      control to the guest kernel. Only then the Linux guest parses the device
      tree so it is possible to avoid unnecessary reboot in most cases.
      
      The device tree diff is a header with an update format version
      (defined as 1 in this patch) followed by a device tree with the properties
      which require update.
      
      If QEMU detects that it has to reboot the guest, it silently does so
      as the guest expects reboot to happen because this is usual pHyp firmware
      behavior.
      
      This defines custom KVMPPC_H_CAS hypercall. The current SLOF already
      has support for it.
      
      This implements stub which returns very basic tree (root node,
      no properties) to the guest.
      
      As the return buffer does not contain any change, no change in behavior is
      expected.
      Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      2a6593cb
    • A
      target-ppc: Implement "compat" CPU option · 6d9412ea
      Alexey Kardashevskiy 提交于
      This adds basic support for the "compat" CPU option. By specifying
      the compat property, the user can manually switch guest CPU mode from
      "raw" to "architected".
      
      This defines feature disable bits which are not used yet as, for example,
      PowerISA 2.07 says if 2.06 mode is selected, the TM bit does not matter -
      transactional memory (TM) will be disabled because 2.06 does not define
      it at all. The same is true for VSX and 2.05 mode. So just setting a mode
      must be ok.
      
      This does not change the existing behavior as the actual compatibility
      mode support is coming in next patches.
      Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru>
      [agraf: fix compilation on 32bit hosts]
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      6d9412ea
    • A
      spapr: Move SMT-related properties out of skeleton fdt · 833d4668
      Alexey Kardashevskiy 提交于
      The upcoming support of the "ibm,client-architecture-support"
      reconfiguration call will be able to change dynamically the number
      of threads per core (SMT mode). From the device tree prospective
      this does not change the number of CPU nodes (as it is one node per
      a CPU core) but affects content and size of the ibm,ppc-interrupt-server#s
      and ibm,ppc-interrupt-gserver#s properties.
      
      This moves ibm,ppc-interrupt-server#s and ibm,ppc-interrupt-gserver#s
      out of the device tree skeleton.
      Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      833d4668
    • A
      spapr: Add ibm, chip-id property in device tree · 10582ff8
      Alexey Kardashevskiy 提交于
      This adds a "ibm,chip-id" property for CPU nodes which should be the same
      for all cores in the same CPU socket. The recent guest kernels use this
      information to associate threads with sockets.
      
      Refer to the kernel commit 256f2d4b463d3030ebc8d2b54f427543814a2bdc
      for more details.
      Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      10582ff8