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  1. 02 6月, 2010 20 次提交
  3. 01 6月, 2010 5 次提交
    • B
      ioapic: improve debugging · 9af9b330
      由 Blue Swirl 提交于 
      Add a DPRINTF macro, use it also to see irq deliveries.
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
      9af9b330
    • A
      Fix leul_to_cpu on big endian hosts · 17e6a53f
      由 Alexander Graf 提交于 
      Commit 213acd2e introduced leul_to_cpu with a special code path for big endian
hosts. Unfortunately that code used preprocessor magic that didn't work.

This patch replaces the explicit ##s by glue() which is proven to work reliably,
enabling me to compile qemu on ppc again.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      17e6a53f
    • L
      arm: fix arm kernel boot for non zero start addr · e03c22a9
      由 Lars Munch 提交于 
      Booting an arm kernel has been broken a while when booting from non zero start
address. This is due to the order of events: board init loads the kernel and
sets register 15 to the start address and then qemu_system_reset reset the cpu
making register 15 zero again.

This patch fixes the usage of the register 15 start address trick in
combination with arm_load_kernel.
Signed-off-by: NLars Munch <lars@segv.dk>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      e03c22a9
    • T
      target-ppc: remove useless line · 0f89cc7b
      由 Thomas Monjalon 提交于 
      This line was a bit clear.
The next lines set or reset this bit (LE) depending of another bit (ILE).
So the first line is useless.
Signed-off-by: NThomas Monjalon <thomas@monjalon.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      0f89cc7b
    • T
      target-ppc: fix RFI by clearing some bits of MSR · c3d420ea
      由 Thomas Monjalon 提交于 
      Since commit 2ada0ed7, "Return From Interrupt" is broken for PPC processors
because some interrupt specifics bits of SRR1 are copied to MSR.

SRR1 is a save of MSR during interrupt.
During RFI, MSR must be restored from SRR1.
But some bits of SRR1 are interrupt-specific and are not used for MSR saving.

This is the specification (ISA 2.06) at chapter 6.4.3 (Interrupt Processing):
"2. Bits 33:36 and 42:47 of SRR1 or HSRR1 are loaded with information specific
    to the interrupt type.
 3. Bits 0:32, 37:41, and 48:63 of SRR1 or HSRR1 are loaded with a copy of the
    corresponding bits of the MSR."

Below is a representation of MSR bits which are not saved:
0:15 16:31 32  33:36    37:41      42:47     48:63
——— | ——— | — X X X X — — — — — X X X X X X | ————
0000 0000 |    7   |   8   |   3   |   F    | 0000

History:
In the initial Qemu implementation (e1833e1f), the mask 0x783F0000 was used for
saving MSR in SRR1. But all the bits 32:47 were cleared during RFI restoring.
This was wrong. The commit 2ada0ed7 explains that this breaks Altivec.
Indeed, bit 38 (for Altivec support) must be saved and restored.
The change of 2ada0ed7 was to restore all the bits of SRR1 to MSR.
But it's also wrong.

Explanation:
As an example, let's see what's happening after a TLB miss.
According to the e300 manual (E300CORERM table 5-6), the TLB miss interrupts
set the bits 44-47 for KEY, I/D, WAY and S/L. These bits are specifics to the
interrupt and must not be copied into MSR at the end of the interrupt.
With the current implementation, a TLB miss overwrite bits POW, TGPR and ILE.

Fix:
It shouldn't be needed to filter-out bits on MSR saving when interrupt occurs.
Specific bits overwrite MSR ones in SRR1.
But at the end of interrupt (RFI), specifics bits must be cleared before
restoring MSR from SRR1. The mask 0x783F0000 apply here.

Discussion:
The bits of the mask 0x783F0000 are cleared after an interrupt.
I cannot find a specification which talks about this
but I assume it is the truth since Linux can run this way.
Maybe it's not perfect but it's better (works for e300).
Signed-off-by: NThomas Monjalon <thomas@monjalon.net>
Acked-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      c3d420ea
  5. 31 5月, 2010 1 次提交
  7. 30 5月, 2010 4 次提交
  9. 29 5月, 2010 10 次提交