1. 22 2月, 2018 7 次提交
    • H
      Fix ast2500 protection register emulation · 5c1d3a2b
      Hugo Landau 提交于
      Some register blocks of the ast2500 are protected by protection key
      registers which require the right magic value to be written to those
      registers to allow those registers to be mutated.
      
      Register manuals indicate that writing the correct magic value to these
      registers should cause subsequent reads from those values to return 1,
      and writing any other value should cause subsequent reads to return 0.
      
      Previously, qemu implemented these registers incorrectly: the registers
      were handled as simple memory, meaning that writing some value x to a
      protection key register would result in subsequent reads from that
      register returning the same value x. The protection was implemented by
      ensuring that the current value of that register equaled the magic
      value.
      
      This modifies qemu to have the correct behaviour: attempts to write to a
      ast2500 protection register results in a transition to 1 or 0 depending
      on whether the written value is the correct magic. The protection logic
      is updated to ensure that the value of the register is nonzero.
      
      This bug caused deadlocks with u-boot HEAD: when u-boot is done with a
      protectable register block, it attempts to lock it by writing the
      bitwise inverse of the correct magic value, and then spinning forever
      until the register reads as zero. Since qemu implemented writes to these
      registers as ordinary memory writes, writing the inverse of the magic
      value resulted in subsequent reads returning that value, leading to
      u-boot spinning forever.
      Signed-off-by: NHugo Landau <hlandau@devever.net>
      Reviewed-by: NCédric Le Goater <clg@kaod.org>
      Acked-by: NAndrew Jeffery <andrew@aj.id.au>
      Message-id: 20180220132627.4163-1-hlandau@devever.net
      [PMM: fixed incorrect code indentation]
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      5c1d3a2b
    • R
      hw/char/stm32f2xx_usart: fix TXE/TC bit handling · f6bfe45a
      Richard Braun 提交于
      I/O currently being synchronous, there is no reason to ever clear the
      SR_TXE bit. However the SR_TC bit may be cleared by software writing
      to the SR register, so set it on each write.
      
      In addition, fix the reset value of the USART status register.
      Signed-off-by: NRichard Braun <rbraun@sceen.net>
      Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com>
      [PMM: removed XXX tag from comment, since it isn't something
       we need to come back and fix in QEMU]
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      f6bfe45a
    • P
      raspi: Add "raspi3" machine type · 1c3db49d
      Pekka Enberg 提交于
      This patch adds a "raspi3" machine type, which can now be selected as
      the machine to run on by users via the "-M" command line option to QEMU.
      
      The machine type does *not* ignore memory transaction failures so we
      likely need to add some dummy devices later when people run something
      more complicated than what I'm using for testing.
      Signed-off-by: NPekka Enberg <penberg@iki.fi>
      [PMM: added #ifdef TARGET_AARCH64 so we don't provide the 64-bit
       board in the 32-bit only arm-softmmu build.]
      Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      1c3db49d
    • P
      target/arm: Fix register definitions for VMIDR and VMPIDR · 36476562
      Peter Maydell 提交于
      The register definitions for VMIDR and VMPIDR have separate
      reginfo structs for the AArch32 and AArch64 registers. However
      the 32-bit versions are wrong:
       * they use offsetof instead of offsetoflow32 to mark where
         the 32-bit value lives in the uint64_t CPU state field
       * they don't mark themselves as ARM_CP_ALIAS
      
      In particular this means that if you try to use an Arm guest CPU
      which enables EL2 on a big-endian host it will assert at reset:
       target/arm/cpu.c:114: cp_reg_check_reset: Assertion `oldvalue == newvalue' failed.
      
      because the reset of the 32-bit register writes to the top
      half of the uint64_t.
      
      Correct the errors in the structures.
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
      ---
      This is necessary for 'make check' to pass on big endian
      systems with the 'raspi3' board enabled, which is the
      first board which has an EL2-enabled-by-default CPU.
      36476562
    • P
      Merge remote-tracking branch 'remotes/mcayland/tags/qemu-openbios-signed' into staging · ff868961
      Peter Maydell 提交于
      Update OpenBIOS images
      
      # gpg: Signature made Thu 22 Feb 2018 08:12:01 GMT
      # gpg:                using RSA key 5BC2C56FAE0F321F
      # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>"
      # Primary key fingerprint: CC62 1AB9 8E82 200D 915C  C9C4 5BC2 C56F AE0F 321F
      
      * remotes/mcayland/tags/qemu-openbios-signed:
        Update OpenBIOS images to 54d959d9 built from submodule.
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      ff868961
    • P
      Merge remote-tracking branch 'remotes/stsquad/tags/pull-softfloat-refactor-210218-1' into staging · 2b78551f
      Peter Maydell 提交于
      This is the re-factor of softfloat:
      
        - shared common code path float16/32/64
        - well commented and easy to follow code
        - added a bunch of float16 support
      
      While some operations are slower the key ones exercised by the
      floating point dbt-bench are the same: https://i.imgur.com/oXNJNql.png
      
      # gpg: Signature made Wed 21 Feb 2018 10:44:14 GMT
      # gpg:                using RSA key FBD0DB095A9E2A44
      # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>"
      # Primary key fingerprint: 6685 AE99 E751 67BC AFC8  DF35 FBD0 DB09 5A9E 2A44
      
      * remotes/stsquad/tags/pull-softfloat-refactor-210218-1: (22 commits)
        fpu/softfloat: re-factor sqrt
        fpu/softfloat: re-factor compare
        fpu/softfloat: re-factor minmax
        fpu/softfloat: re-factor scalbn
        fpu/softfloat: re-factor int/uint to float
        fpu/softfloat: re-factor float to int/uint
        fpu/softfloat: re-factor round_to_int
        fpu/softfloat: re-factor muladd
        fpu/softfloat: re-factor div
        fpu/softfloat: re-factor mul
        fpu/softfloat: re-factor add/sub
        fpu/softfloat: define decompose structures
        fpu/softfloat: move the extract functions to the top of the file
        fpu/softfloat: improve comments on ARM NaN propagation
        include/fpu/softfloat: add some float16 constants
        include/fpu/softfloat: implement float16_set_sign helper
        include/fpu/softfloat: implement float16_chs helper
        include/fpu/softfloat: implement float16_abs helper
        target/*/cpu.h: remove softfloat.h
        fpu/softfloat-types: new header to prevent excessive re-builds
        ...
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      2b78551f
    • M
  2. 21 2月, 2018 22 次提交
  3. 20 2月, 2018 11 次提交