- 27 9月, 2017 8 次提交
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由 Benjamin Herrenschmidt 提交于
Apple uses an IBM MPIC2A without timers, it has 64 sources. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Benjamin Herrenschmidt 提交于
The timing register exists on all variants of MacIO IDE, we just store and return its value. The interrupts register only exists on KeyLargo but it doesn't hurt to have it. The lack of this register causes MacOS X to hangs under some circumstances. Both are 32-bit only. The HW might support smaller access sizes but no known OS uses them. Because the core IDE subsystem doesn't provide us with a way to query the main (level) interrupt state, nor do we have a way to know that DBDMA issued a (edge) interrupt, we reflect both through a private pair of qirq's in order to maintain the register state. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Benjamin Herrenschmidt 提交于
This completely reworks the handling of the control register according to my understanding of the HW and the spec. It should (hopefully ... still testing) fix a number of issues most notably cases of MacOS hanging. Also update dbdma_unassigned_rw() and dbdma_unassigned_flush() to have the expected behaviour now that flush is handled slightly differently. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Benjamin Herrenschmidt 提交于
We use 900Mhz, otherwise MacOS X 10.5 refuses to install. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Mark Cave-Ayland 提交于
Signed-off-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 BALATON Zoltan 提交于
These registers are present in 440 SoCs (and maybe in others too) and U-Boot accesses them when printing register info. We don't emulate these but add them to avoid crashing when they are read or written. Signed-off-by: NBALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 BALATON Zoltan 提交于
Some PPC SoCs have an EHCI with OHCI companion USB controller. Add a new type for this similar to types used for other embedded SoCs. Signed-off-by: NBALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NGerd Hoffmann <kraxel@redhat.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 BALATON Zoltan 提交于
Some PPC SoCs have an EHCI with OHCI companion USB controller. To emulate this allow the sysbus version of OHCI to be used as a companion. Signed-off-by: NBALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NGerd Hoffmann <kraxel@redhat.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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- 26 9月, 2017 5 次提交
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由 Thomas Huth 提交于
QEMU currently aborts if you try to use the device at the command line: $ ppc64-softmmu/qemu-system-ppc64 -S -machine prep -device pc87312 Unexpected error in qemu_chr_fe_init() at chardev/char-fe.c:222: qemu-system-ppc64: -device pc87312: Device 'parallel0' is in use Aborted (core dumped) It uses parallel_hds in its realize function, so I can not be instantiated by the user again. Signed-off-by: NThomas Huth <thuth@redhat.com> Reviewed-by: NHervé Poussineau <hpoussin@reactos.org> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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由 Thomas Huth 提交于
The virtio-gpu-pci device is already in the display category, so the virtio-gpu-device should be there, too. Signed-off-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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由 Liang Yan 提交于
It may be better to add a trace event to monitor the last moment of a key event from QEMU to guest VM Signed-off-by: NLiang Yan <lyan@suse.com> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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由 KONRAD Frederic 提交于
This device is private and is created once per aux-bus. So don't allow the user to create one from command-line. Reported-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NKONRAD Frederic <frederic.konrad@adacore.com> Reviewed-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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由 Kamil Rytarowski 提交于
This change fixes conflict with the DragonFly BSD headers. Signed-off-by: NKamil Rytarowski <n54@gmx.com> Reviewed-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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- 22 9月, 2017 6 次提交
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由 John Snow 提交于
Apparently GCC gets bent over comparing enum values against zero. Replace the conditional with something less readable. Tested-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: NJohn Snow <jsnow@redhat.com> Reviewed-by: NStefan Hajnoczi <stefanha@redhat.com> Message-id: 20170921013821.1673-1-jsnow@redhat.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Fam Zheng 提交于
Signed-off-by: NFam Zheng <famz@redhat.com> Message-Id: <20170907082918.7299-10-famz@redhat.com> Reviewed-by: NGerd Hoffmann <kraxel@redhat.com> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: NFam Zheng <famz@redhat.com>
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由 Fam Zheng 提交于
Signed-off-by: NFam Zheng <famz@redhat.com> Message-Id: <20170907082918.7299-9-famz@redhat.com> Reviewed-by: NGerd Hoffmann <kraxel@redhat.com> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: NFam Zheng <famz@redhat.com>
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由 Fam Zheng 提交于
Signed-off-by: NFam Zheng <famz@redhat.com> Message-Id: <20170907082918.7299-8-famz@redhat.com> Reviewed-by: NGerd Hoffmann <kraxel@redhat.com> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: NFam Zheng <famz@redhat.com>
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由 Alexey Kardashevskiy 提交于
Since FlatViews are shared now and ASes not, this gets rid of address_space_init_shareable(). This should cause no behavioural change. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Message-Id: <20170921085110.25598-17-aik@ozlabs.ru> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Alexey Kardashevskiy 提交于
FlatView's will be shared between AddressSpace's and subpage_t and MemoryRegionSection cannot store AS anymore, hence this change. In particular, for: typedef struct subpage_t { MemoryRegion iomem; - AddressSpace *as; + FlatView *fv; hwaddr base; uint16_t sub_section[]; } subpage_t; struct MemoryRegionSection { MemoryRegion *mr; - AddressSpace *address_space; + FlatView *fv; hwaddr offset_within_region; Int128 size; hwaddr offset_within_address_space; bool readonly; }; This should cause no behavioural change. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Message-Id: <20170921085110.25598-7-aik@ozlabs.ru> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 21 9月, 2017 21 次提交
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由 Subbaraya Sundeep 提交于
Emulated Emcraft's Smartfusion2 System On Module starter kit. Signed-off-by: NSubbaraya Sundeep <sundeep.lkml@gmail.com> Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170920201737.25723-6-f4bug@amsat.org [PMD: drop cpu_model to directly use cpu type] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Subbaraya Sundeep 提交于
Smartfusion2 SoC has hardened Microcontroller subsystem and flash based FPGA fabric. This patch adds support for Microcontroller subsystem in the SoC. Signed-off-by: NSubbaraya Sundeep <sundeep.lkml@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170920201737.25723-5-f4bug@amsat.org [PMD: drop cpu_model to directly use cpu type, check m3clk non null] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Subbaraya Sundeep 提交于
Modelled Microsemi's Smartfusion2 SPI controller. Signed-off-by: NSubbaraya Sundeep <sundeep.lkml@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Tested-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170920201737.25723-4-f4bug@amsat.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Subbaraya Sundeep 提交于
Added Sytem register block of Smartfusion2. This block has PLL registers which are accessed by guest. Signed-off-by: NSubbaraya Sundeep <sundeep.lkml@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Acked-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170920201737.25723-3-f4bug@amsat.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Subbaraya Sundeep 提交于
Modelled System Timer in Microsemi's Smartfusion2 Soc. Timer has two 32bit down counters and two interrupts. Signed-off-by: NSubbaraya Sundeep <sundeep.lkml@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Acked-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170920201737.25723-2-f4bug@amsat.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Don't use old_mmio in the memory region ops struct. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505580378-9044-7-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Don't use old_mmio in the memory region ops struct. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505580378-9044-6-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Don't use the old_mmio struct in memory region ops. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505580378-9044-5-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Don't use the old_mmio in the memory region ops struct. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505580378-9044-4-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Drop the use of old_mmio in the omap2_gpio memory ops. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505580378-9044-3-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Update the static_ops functions to use new-style mmio rather than the legacy old_mmio functions. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505580378-9044-2-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Update armv7m_nvic_acknowledge_irq() and armv7m_nvic_complete_irq() to handle banked exceptions: * acknowledge needs to use the correct vector, which may be in sec_vectors[] * acknowledge needs to return to its caller whether the exception should be taken to secure or non-secure state * complete needs its caller to tell it whether the exception being completed is a secure one or not Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-20-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Handle banking of SHCSR: some register bits are banked between Secure and Non-Secure, and some are only accessible to Secure. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-19-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The ICSR NVIC register is banked for v8M. This doesn't require any new state, but it does mean that some bits are controlled by BFHNFNMINS and some bits must work with the correct banked exception. There is also a new in v8M PENDNMICLR bit. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-18-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Now that we have a banked FAULTMASK register and banked exceptions, we can implement the correct check in cpu_mmu_index() for whether the MPU_CTRL.HFNMIENA bit's effect should apply. This bit causes handlers which have requested a negative execution priority to run with the MPU disabled. In v8M the test has to check this for the current security state and so takes account of banking. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-17-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Update nvic_exec_prio() to support the v8M changes: * BASEPRI, FAULTMASK and PRIMASK are all banked * AIRCR.PRIS can affect NS priorities * AIRCR.BFHFNMINS affects FAULTMASK behaviour These changes mean that it's no longer possible to definitely say that if FAULTMASK is set it overrides PRIMASK, and if PRIMASK is set it overrides BASEPRI (since if PRIMASK_NS is set and AIRCR.PRIS is set then whether that 0x80 priority should take effect or the priority in BASEPRI_S depends on the value of BASEPRI_S, for instance). So we switch to the same approach used by the pseudocode of working through BASEPRI, PRIMASK and FAULTMASK and overriding the previous values if needed. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-16-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
If AIRCR.BFHFNMINS is clear, then although NonSecure HardFault can still be pended via SHCSR.HARDFAULTPENDED it mustn't actually preempt execution. The simple way to achieve this is to clear the enable bit for it, since the enable bit isn't guest visible. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-15-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
In v7M, the fixed-priority exceptions are: Reset: -3 NMI: -2 HardFault: -1 In v8M, this changes because Secure HardFault may need to be prioritised above NMI: Reset: -4 Secure HardFault if AIRCR.BFHFNMINS == 1: -3 NMI: -2 Secure HardFault if AIRCR.BFHFNMINS == 0: -1 NonSecure HardFault: -1 Make these changes, including support for changing the priority of Secure HardFault as AIRCR.BFHFNMINS changes. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-14-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
When escalating to HardFault, we must go into Lockup if we can't take the synchronous HardFault because the current execution priority is already at or below the priority of HardFault. In v7M HF is always priority -1 so a simple < 0 comparison sufficed; in v8M the priority of HardFault can vary depending on whether it is a Secure or NonSecure HardFault, so we must check against the priority of the HardFault exception vector we're about to use. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-13-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
In armv7m_nvic_set_pending() we have to compare the priority of an exception against the execution priority to decide whether it needs to be escalated to HardFault. In the specification this is a comparison against the exception's group priority; for v7M we implemented it as a comparison against the raw exception priority because the two comparisons will always give the same answer. For v8M the existence of AIRCR.PRIS and the possibility of different PRIGROUP values for secure and nonsecure exceptions means we need to explicitly calculate the vector's group priority for this check. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-12-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Make the set_prio() function take a bool indicating whether to pend the secure or non-secure version of a banked interrupt, and use this to implement the correct banking semantics for the SHPR registers. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-11-git-send-email-peter.maydell@linaro.org
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