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  1. 18 4月, 2016 1 次提交
    • T
      ppc: Fix the bad exception NIP value and the range check in LSWX · 537d3e8e
      由 Thomas Huth 提交于 
      The range checks in the LSWX instruction are completely insufficient:
They do not take the wrap-around case into account, and the check
"reg < rx" should be "reg <= rx" instead. Fix it by using the new
lsw_reg_in_range() helper function that is already used for LSWI, too.

Then there is a second problem: In case the INVAL exception is generated,
the NIP value is wrong, it currently points to the instruction before
the LSWX instruction. This is because gen_lswx() already decreases the
NIP value by 4 (to be prepared for page fault exceptions), and
powerpc_excp() later decreases it again by 4 while handling the program
exception. So to get this right, we've got to undo the "- 4" from
gen_lswx() here before calling helper_raise_exception_err().
Signed-off-by: NThomas Huth <thuth@redhat.com>
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      537d3e8e
  3. 29 1月, 2016 1 次提交
    • P
      ppc: Clean up includes · 0d75590d
      由 Peter Maydell 提交于 
      Clean up includes so that osdep.h is included first and headers
which it implies are not included manually.

This commit was created with scripts/clean-includes.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1453832250-766-6-git-send-email-peter.maydell@linaro.org
      0d75590d
  5. 12 11月, 2015 1 次提交
  7. 07 1月, 2015 1 次提交
  9. 16 6月, 2014 1 次提交
  11. 05 6月, 2014 1 次提交
  13. 29 5月, 2014 1 次提交
  15. 26 10月, 2013 1 次提交
  17. 27 4月, 2013 1 次提交
  19. 22 3月, 2013 1 次提交
  21. 01 2月, 2013 1 次提交
    • A
      PPC: Unify dcbzl code path · 8e33944f
      由 Alexander Graf 提交于 
      The bit that makes a dcbz instruction a dcbzl instruction was declared as
reserved in ppc32 ISAs. However, hardware simply ignores the bit, making
code valid if it simply invokes dcbzl instead of dcbz even on 750 and G4.

Thus, mark the bit as unreserved so that we properly emulate a simple dcbz
in case we're running on non-G5s.

While at it, also refactor the code to check the 970 special case during
runtime. This way we don't need to differenciate between a 970 dcbz and
any other dcbz anymore. We also allow for future improvements to add e500mc
dcbz handling.
Reported-by: NAmadeusz Sławiński <amade@asmblr.net>
Signed-off-by: NAlexander Graf <agraf@suse.de>
      8e33944f
  23. 19 12月, 2012 2 次提交
  25. 16 12月, 2012 1 次提交
  27. 24 6月, 2012 10 次提交
  29. 14 4月, 2012 1 次提交
  31. 15 3月, 2012 1 次提交
  33. 02 2月, 2012 6 次提交
  35. 02 12月, 2011 1 次提交
  37. 01 10月, 2011 1 次提交
  39. 07 8月, 2011 1 次提交
  41. 30 7月, 2011 1 次提交
    • B
      exec.h cleanup · 3e457172
      由 Blue Swirl 提交于 
      Move softmmu_exec.h include directives from target-*/exec.h to
target-*/op_helper.c. Move also various other stuff only used in
op_helper.c there.

Define global env in dyngen-exec.h.

For i386, move wrappers for segment and FPU helpers from user-exec.c
to op_helper.c. Implement raise_exception_err_env() to handle dynamic
CPUState. Move the function declarations to cpu.h since they can be
used outside of op_helper.c context.

LM32, s390x, UniCore32: remove unused cpu_halted(), regs_to_env() and
env_to_regs().

ARM: make raise_exception() static.

Convert
#include "exec.h"
to
#include "cpu.h"
#include "dyngen-exec.h"
and remove now unused target-*/exec.h.
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
      3e457172
  43. 27 6月, 2011 1 次提交
  45. 17 6月, 2011 2 次提交
    • A
      PPC: move TLBs to their own arrays · 1c53accc
      由 Alexander Graf 提交于 
      Until now, we've created a union over multiple different TLB types and
allocated that union. While it's a waste of memory (and cache) to allocate
TLB information for a TLB type with much information when you only need
little, it also inflicts another issue.

With the new KVM API, we can now share the TLB between KVM and qemu, but
for that to work we need to have both be in the same layout. We can't just
stretch it over to fit some internal different TLB representation.

Hence this patch moves all TLB types to their own array, allowing us to only
address and allocate exactly the boundaries required for the specific TLB
type at hand.
Signed-off-by: NAlexander Graf <agraf@suse.de>
      1c53accc
    • A
      PPC: E500: Use MAS registers instead of internal TLB representation · d1e256fe
      由 Alexander Graf 提交于 
      The natural format for e500 cores to do TLB manipulation with are the MAS
registers. Instead of converting them into some internal representation
and back again when the guest reads them, we can just keep the data
identical to the way the guest passed it to us.

The main advantage of this approach is that we're getting closer to being
able to share MMU data with KVM using shared memory, so that we don't need
to copy lots of MMU data back and forth all the time. For this to work
however, another patch is required that gets rid of the TLB union, as that
destroys our memory layout that needs to be identical with the kernel one.
Signed-off-by: NAlexander Graf <agraf@suse.de>
      d1e256fe
  47. 03 6月, 2011 1 次提交