- 12 6月, 2015 5 次提交
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由 Leon Alrae 提交于
Implement MTHC0 and MFHC0 instructions. In MIPS32 they are used to access upper word of extended to 64-bits CP0 registers. In MIPS64, when CP0 destination register specified is the EntryLo0 or EntryLo1, bits 1:0 of the GPR appear at bits 31:30 of EntryLo0 or EntryLo1. This is to compensate for RI and XI, which were shifted to bits 63:62 by MTC0 to EntryLo0 or EntryLo1. Therefore creating separate functions for EntryLo0 and EntryLo1. Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Leon Alrae 提交于
CP0.PageGrain.ELPA enables support for large physical addresses. This field is encoded as follows: 0: Large physical address support is disabled. 1: Large physical address support is enabled. If this bit is a 1, the following changes occur to coprocessor 0 registers: - The PFNX field of the EntryLo0 and EntryLo1 registers is writable and concatenated with the PFN field to form the full page frame number. - Access to optional COP0 registers with PA extension, LLAddr, TagLo is defined. P5600 can operate in 32-bit or 40-bit Physical Address Mode. Therefore if XPA is disabled (CP0.PageGrain.ELPA = 0) then assume 32-bit Address Mode. In MIPS64 assume 36 as default PABITS (when CP0.PageGrain.ELPA = 0). env->PABITS value is constant and indicates maximum PABITS available on a core, whereas env->PAMask is calculated from env->PABITS and is also affected by CP0.PageGrain.ELPA. Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Leon Alrae 提交于
Update tlb->PFN to contain PFN concatenated with PFNX. PFNX is 0 if large physical address is not supported. Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Leon Alrae 提交于
Extend EntryLo0, EntryLo1, LLAddr and TagLo from 32 to 64 bits in MIPS32. Introduce gen_move_low32() function which moves low 32 bits from 64-bit temp to GPR; it sign extends 32-bit value on MIPS64 and truncates on MIPS32. Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Leon Alrae 提交于
CP0.EntryLo bits 31:30 have to be cleared. Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
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- 11 6月, 2015 23 次提交
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由 Hervé Poussineau 提交于
Documentation is not clear of what happens when doing a hardware reset, but firmware expect all registers to be zero unless specified otherwise. This fixes reboot on MIPS Magnum. Signed-off-by: NHervé Poussineau <hpoussin@reactos.org> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Hervé Poussineau 提交于
Don't write more than the field width, which is always 16 bit. Fixes network in NetBSD 5.1/arc Signed-off-by: NHervé Poussineau <hpoussin@reactos.org> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Hervé Poussineau 提交于
Signed-off-by: NHervé Poussineau <hpoussin@reactos.org> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Hervé Poussineau 提交于
Signed-off-by: NLaurent Vivier <laurent@vivier.eu> Signed-off-by: NHervé Poussineau <hpoussin@reactos.org> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Hervé Poussineau 提交于
Signed-off-by: NLaurent Vivier <laurent@vivier.eu> Signed-off-by: NHervé Poussineau <hpoussin@reactos.org> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Hervé Poussineau 提交于
Signed-off-by: NHervé Poussineau <hpoussin@reactos.org> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Hervé Poussineau 提交于
Signed-off-by: NHervé Poussineau <hpoussin@reactos.org> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Hervé Poussineau 提交于
Signed-off-by: NHervé Poussineau <hpoussin@reactos.org> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Hervé Poussineau 提交于
Signed-off-by: NHervé Poussineau <hpoussin@reactos.org> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Hervé Poussineau 提交于
Remove also unneeded debug logs. Signed-off-by: NHervé Poussineau <hpoussin@reactos.org> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Hervé Poussineau 提交于
Signed-off-by: NHervé Poussineau <hpoussin@reactos.org> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Hervé Poussineau 提交于
Signed-off-by: NHervé Poussineau <hpoussin@reactos.org> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Hervé Poussineau 提交于
Now that rc4030 internally uses an AddressSpace for DMA handling, make its root memory region public. This is especially usefull for dp8393x netcard, which now uses well known QEMU types and methods. Signed-off-by: NHervé Poussineau <hpoussin@reactos.org> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Hervé Poussineau 提交于
Add a new memory region in system address space where DMA address space definition (the 'translation table') belongs, so we can update on the fly the DMA address space. Signed-off-by: NHervé Poussineau <hpoussin@reactos.org> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Hervé Poussineau 提交于
Remove now useless device models from other MIPS configurations We're now compiling 12 files less than before. Signed-off-by: NHervé Poussineau <hpoussin@reactos.org> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Leon Alrae 提交于
ERETNC is identical to ERET except that an ERETNC will not clear the LLbit that is set by execution of an LL instruction, and thus when placed between an LL and SC sequence, will never cause the SC to fail. Presence of ERETNC is denoted by the Config5.LLB. Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Yongbok Kim 提交于
MIPS SIMD Architecture vector loads and stores require misalignment support. MSA Memory access should work as an atomic operation. Therefore, it has to check validity of all addresses for a vector store access if it is spanning into two pages. Separating helper functions for each data format as format is known in translation. To use mmu_idx from cpu_mmu_index() instead of calculating it from hflag. Removing save_cpu_state() call in translation because it is able to use cpu_restore_state() on fault as GETRA() is passed. Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com> [leon.alrae@imgtec.com: remove unused do_* functions] Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Yongbok Kim 提交于
Probe for whether the specified guest write access is permitted. If it is not permitted then an exception will be taken in the same way as if this were a real write access (and we will not return). Otherwise the function will return, and there will be a valid entry in the TLB for this access. Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Yongbok Kim 提交于
Release 6 requires misaligned memory access support for all ordinary memory access instructions (for example, LW/SW, LWC1/SWC1). However misaligned support is not provided for certain special memory accesses such as atomics (for example, LL/SC). Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Paul Burton 提交于
Commit 94c2b6af (mips_malta: support up to 2GiB RAM) provided support for using over 256MB of RAM with the MIPS Malta board, including capping the memsize variable that QEMUs pseudo-bootloader provides to the kernel at 256MB in order to match YAMON. It didn't however provide the ememsize variable which kernels supporting memory outside of the unmapped address spaces (ie. EVA or highmem) may use to determine the true size of the RAM present in the system. Set ememsize to the size of RAM so that such kernels may use all available memory without the user having to manually specifying its size & location. Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Leon Alrae 提交于
This relatively small architectural feature adds the following: FIR.FREP: Read-only. If FREP=1, then Config5.FRE and Config5.UFE are available. Config5.FRE: When enabled all single-precision FP arithmetic instructions, LWC1/LWXC1/MTC1, SWC1/SWXC1/MFC1 cause a Reserved Instructions exception. Config5.UFE: Allows user to write/read Config5.FRE using CTC1/CFC1 instructions. Enable the feature in MIPS64R6-generic CPU. Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Leon Alrae 提交于
Move the "Tests" group of functions so that gen_load_fpr32() and gen_store_fpr32() can use generate_exception(). Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Peter Maydell 提交于
stdvga: factor out mmio subregion init virtio-gpu: add virtio gpu core code, 2d mode # gpg: Signature made Wed Jun 10 10:03:11 2015 BST using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-vga-20150610-1: virtio-gpu/2d: add virtio gpu core code virtio: update headers, add virtio-gpu (2d) stdvga: factor out mmio subregion init stdvga: pass VGACommonState instead of PCIVGAState stdvga: fix offset in pci_vga_ioport_read Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 10 6月, 2015 12 次提交
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由 Peter Maydell 提交于
fw_cfg: drop write support, qemu cmdline support, bugfixes. bios-tables-test: fix smbios test. # gpg: Signature made Wed Jun 10 07:29:53 2015 BST using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-fw_cfg-20150610-1: bios-tables-test: handle false-positive smbios signature matches fw_cfg: insert fw_cfg file blobs via qemu cmdline fw_cfg: prohibit insertion of duplicate fw_cfg file names fw_cfg: prevent selector key conflict fw_cfg: remove support for guest-side data writes fw_cfg: fix FW_CFG_BOOT_DEVICE update on ppc and sparc fw_cfg: add fw_cfg_modify_i16 (update) method QemuOpts: increase number of vm_config_groups Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Initial VFIO platform device support, v2 (Eric Auger, et al.) # gpg: Signature made Tue Jun 9 15:25:40 2015 BST using RSA key ID 3BB08B22 # gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>" # gpg: aka "Alex Williamson <alex@shazbot.org>" # gpg: aka "Alex Williamson <alwillia@redhat.com>" # gpg: aka "Alex Williamson <alex.l.williamson@gmail.com>" * remotes/awilliam/tags/vfio-update-20150609.0: hw/vfio/platform: calxeda xgmac device hw/vfio/platform: add irq assignment hw/vfio/platform: vfio-platform skeleton Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Merge remote-tracking branch 'remotes/stefanha/tags/CVE-2015-3209-pcnet-tx-buffer-fix-pull-request' into staging # gpg: Signature made Wed Jun 10 15:04:11 2015 BST using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" * remotes/stefanha/tags/CVE-2015-3209-pcnet-tx-buffer-fix-pull-request: pcnet: force the buffer access to be in bounds during tx Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Petr Matousek 提交于
4096 is the maximum length per TMD and it is also currently the size of the relay buffer pcnet driver uses for sending the packet data to QEMU for further processing. With packet spanning multiple TMDs it can happen that the overall packet size will be bigger than sizeof(buffer), which results in memory corruption. Fix this by only allowing to queue maximum sizeof(buffer) bytes. This is CVE-2015-3209. [Fixed 3-space indentation to QEMU's 4-space coding standard. --Stefan] Signed-off-by: NPetr Matousek <pmatouse@redhat.com> Reported-by: NMatt Tait <matttait@google.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NStefan Hajnoczi <stefanha@redhat.com> Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>
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由 Gerd Hoffmann 提交于
This patch adds the core code for virtio gpu emulation, covering 2d support. Written by Dave Airlie and Gerd Hoffmann. Signed-off-by: NDave Airlie <airlied@redhat.com> Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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由 Gerd Hoffmann 提交于
Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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由 Gerd Hoffmann 提交于
Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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由 Gerd Hoffmann 提交于
Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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由 Gerd Hoffmann 提交于
Simliar to pci_vga_ioport_write. Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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由 Gabriel L. Somlo 提交于
It has been reported that sometimes the .rodata section of SeaBIOS, containing the constant string against which the SMBIOS signature ends up being compared, also falls within the guest f-segment. In that case, the test obviously fails, unless we continue searching for the *real* SMBIOS entry point. Rather than stopping at the first match for the SMBIOS signature ("_SM_") in the f-segment (0xF0000-0xFFFFF), continue scanning until either a valid entry point table is found, or the f-segment has been exhausted. Reported-by: NBruce Rogers <brogers@suse.com> Signed-off-by: NGabriel Somlo <somlo@cmu.edu> Tested-by: NBruce Rogers <brogers@suse.com> Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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由 Gabriel L. Somlo 提交于
Allow user supplied files to be inserted into the fw_cfg device before starting the guest. Since fw_cfg_add_file() already disallows duplicate fw_cfg file names, qemu will exit with an error message if the user supplies multiple blobs with the same fw_cfg file name, or if a blob name collides with a fw_cfg name programmatically added from within the QEMU source code. A warning message will be printed if the fw_cfg item name does not begin with the prefix "opt/", which is recommended for external, user provided blobs. Signed-off-by: NGabriel Somlo <somlo@cmu.edu> Reviewed-by: NLaszlo Ersek <lersek@redhat.com> Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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由 Gabriel L. Somlo 提交于
Exit with an error (instead of simply logging a trace event) whenever the same fw_cfg file name is added multiple times via one of the fw_cfg_add_file[_callback]() host-side API calls. Signed-off-by: NGabriel Somlo <somlo@cmu.edu> Reviewed-by: NLaszlo Ersek <lersek@redhat.com> Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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