1. 09 9月, 2015 3 次提交
    • P
      hw/intc/arm_gic: Fix handling of GICC_APR<n>, GICC_NSAPR<n> registers · 51fd06e0
      Peter Maydell 提交于
      A GICv2 has both GICC_APR<n> and GICC_NSAPR<n> registers, with
      the latter holding the active priority bits for Group 1 interrupts
      (usually Nonsecure interrupts), and the Nonsecure view of the
      GICC_APR<n> is the second half of the GICC_NSAPR<n> registers.
      Turn our half-hearted implementation of APR<n> into a proper
      implementation of both APR<n> and NSAPR<n>:
      
       * Add the underlying state for NSAPR<n>
       * Make sure APR<n> aren't visible for pre-GICv2
       * Implement reading of NSAPR<n>
       * Make non-secure reads of APR<n> behave correctly
       * Implement writing to APR<n> and NSAPR<n>
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      Message-id: 1438089748-5528-4-git-send-email-peter.maydell@linaro.org
      51fd06e0
    • P
      hw/intc/arm_gic: Running priority is group priority, not full priority · df92cfa6
      Peter Maydell 提交于
      Priority values for the GIC are divided into a "group priority"
      and a "subpriority" (with the division being determined by the
      binary point register). The running priority is only determined
      by the group priority of the active interrupts, not the
      subpriority. In particular, this means that there can't be more
      than one active interrupt at any particular group priority.
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      Message-id: 1438089748-5528-3-git-send-email-peter.maydell@linaro.org
      df92cfa6
    • P
      armv7m_nvic: Implement ICSR without using internal GIC state · b06c262b
      Peter Maydell 提交于
      Change the implementation of the Interrupt Control and State Register
      in the v7M NVIC to not use the running_irq and last_active internal
      state fields in the GIC. These fields don't correspond to state in
      a real GIC and will be removed soon.
      The changes to the ICSR are:
       * the VECTACTIVE field is documented as identical to the IPSR[8:0]
         field, so implement it that way
       * implement RETTOBASE via looking at the active state bits
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      Message-id: 1438089748-5528-2-git-send-email-peter.maydell@linaro.org
      b06c262b
  2. 08 9月, 2015 2 次提交
  3. 07 9月, 2015 35 次提交