- 18 6月, 2014 8 次提交
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由 Paolo Bonzini 提交于
This will be necessary later to recognize the case where a request has both dataout and datain. Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
MegaSAS emulation is not IOMMU-friendly. Fix this by switching to pci_dma_* functions. Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Alexey Kardashevskiy 提交于
This makes scsi_command_name() public. This makes use of scsi_command_name() in debug output for scsi-disk and spapr-vscsi host bus adapter. Before this, SCSI used to print hex numbers instead of human-friendly strings. This adds GET_EVENT_STATUS_NOTIFICATION and READ_DISC_INFORMATION to the list of SCSI commands supported by scsi_command_name(). Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Ulrich Obergfell 提交于
This patch fixes a bug in scsi_block_new_request() that was introduced by commit 137745c5. If the host cache is used - i.e. if BDRV_O_NOCACHE is _not_ set - the 'break' statement needs to be executed to 'fall back' to SG_IO. Cc: qemu-stable@nongnu.org Signed-off-by: NUlrich Obergfell <uobergfe@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paul Janzen 提交于
In scsi-disk.c, if you #define DEBUG_SCSI=1, you get: hw/scsi/scsi-disk.c: In function 'scsi_disk_emulate_command': hw/scsi/scsi-disk.c:2018: error: 'SCSIRequest' has no member named 'buf' Change the debugging statement to match the actual value tested. Signed-off-by: NPaul Janzen <pcj@pauljanzen.org> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Peter Lieven 提交于
this patch changes the driver to uses 16 Byte CDBs for READ/WRITE only if the target requires 64bit lba addressing. On one hand this saves 6 bytes in each PDU on the other hand it seems that 10 Byte CDBs seems to be much better supported and tested as a recent issue I had with a major storage supplier lined out. For WRITESAME the logic is a bit more tricky as WRITESAME10 with UNMAP was added really late. Thus a fallback to WRITESAME16 is possible if it supports UNMAP and WRITESAME10 not. Signed-off-by: NPeter Lieven <pl@kamp.de> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Peter Lieven 提交于
it might happen in the future that a function directly invokes its callback. In this case we end up in a segfault because the iTask is gone when the BH is scheduled. Signed-off-by: NPeter Lieven <pl@kamp.de> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Peter Lieven 提交于
this patch adds handling of BUSY status reponse from an iSCSI target. Currently, we fail with -EIO in case of SCSI_STATUS_BUSY while the obvious reaction would be to retry the operation after some time. The retry time is randomly choosen from a range with exponential growth increasing with each retry. This patch includes most of the changes by a an upcoming patch from Stefan Hajnoczi: iscsi: implement .bdrv_detach/attach_aio_context() because I also need the reference to the aio_context for the retry timer to work. I included the changes to maintain better mergeability. Signed-off-by: NPeter Lieven <pl@kamp.de> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 17 6月, 2014 1 次提交
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由 Peter Maydell 提交于
Patch queue for ppc - 2014-06-16 This pull request brings a lot of fun things. Among others we have - e500: u-boot firmware support - sPAPR: magic page enablement - sPAPR: add "compat" CPU option to support older guests - sPAPR: refactorings in preparation for VFIO - POWER8 live migration - mac99: expose bus frequency - little endian core dump, gdb and disas support - new ppc64le-linux-user target - DFP emulation - bug fixes # gpg: Signature made Mon 16 Jun 2014 12:28:32 BST using RSA key ID 03FEDC60 # gpg: Can't check signature: public key not found * remotes/agraf/tags/signed-ppc-for-upstream: (156 commits) spapr_pci: Advertise MSI quota PPC: KVM: Make pv hcall endian agnostic powerpc: use float64 for frsqrte spapr: Add kvm-type property spapr: Create SPAPRMachine struct linux-user: Tell guest about big host page sizes spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE spapr_hcall: Split h_set_mode() target-ppc: Enable DABRX SPR and limit it to <=POWER7 target-ppc: Enable PPR and VRSAVE SPRs migration target-ppc: Add POWER8's Event Based Branch (EBB) control SPRs KVM: target-ppc: Enable TM state migration target-ppc: Add POWER8's TM SPRs target-ppc: Add POWER8's MMCR2/MMCRS SPRs target-ppc: Enable FSCR facility check for TAR target-ppc: Add POWER8's FSCR SPR target-ppc: Add POWER8's TIR SPR target-ppc: Refactor class init for POWER7/8 target-ppc: Switch POWER7/8 classes to use correct PMU SPRs target-ppc: Make use of gen_spr_power5p_lpar() for POWER7/8 ... Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 16 6月, 2014 31 次提交
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由 Paolo Bonzini 提交于
Duplicate removal was added to extract-libs in order to avoid including the same library multiple times into the linking command line; this could potentially happen when using "foo.mo-libs" (which adds the library to all components, causing it to appear N times if the module is composed of N objects). However, sorting and removing duplicates causes problems with static linking, and also with space-separated linker options as found in some Mac OS X packaging systems. Furthermore, the "optimization" is really a non-problem since we do not expect .mo modules to be composed of many files. Reported-by: NSean Bruno <sbruno@ignoranthack.me> Tested-by: NSean Bruno <sbruno@ignoranthack.me> Reviewed-by: NFam Zheng <famz@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Message-id: 1402929805-16836-1-git-send-email-pbonzini@redhat.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Block pull request # gpg: Signature made Mon 16 Jun 2014 12:22:22 BST using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" * remotes/stefanha/tags/block-pull-request: (39 commits) QemuOpts: cleanup tmp 'allocated' member from QemuOptsList cleanup QEMUOptionParameter vpc.c: replace QEMUOptionParameter with QemuOpts vmdk.c: replace QEMUOptionParameter with QemuOpts vhdx.c: replace QEMUOptionParameter with QemuOpts vdi.c: replace QEMUOptionParameter with QemuOpts ssh.c: replace QEMUOptionParameter with QemuOpts sheepdog.c: replace QEMUOptionParameter with QemuOpts rbd.c: replace QEMUOptionParameter with QemuOpts raw_bsd.c: replace QEMUOptionParameter with QemuOpts raw-win32.c: replace QEMUOptionParameter with QemuOpts raw-posix.c: replace QEMUOptionParameter with QemuOpts qed.c: replace QEMUOptionParameter with QemuOpts qcow2.c: replace QEMUOptionParameter with QemuOpts QemuOpts: export qemu_opt_find qcow.c: replace QEMUOptionParameter with QemuOpts nfs.c: replace QEMUOptionParameter with QemuOpts iscsi.c: replace QEMUOptionParameter with QemuOpts gluster.c: replace QEMUOptionParameter with QemuOpts cow.c: replace QEMUOptionParameter with QemuOpts ... Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Badari Pulavarty 提交于
Hotplug of multiple disks fails due to MSI vector quota check. Number of MSI vectors default to 8 allowing only 4 devices. This happens on RHEL6.5 guest. RHEL7 and SLES11 guests fallback to INTX. One way to workaround the issue is to increase total MSIs, so that MSI quota check allows us to hotplug multiple disks. This sets the quota to the maximum number of interupts XICS has which is 1024 now (XICS_IRQS). This moves XICS_IRQS from spapr.c to xics.h for wider visibility. Signed-off-by: NBadari Pulavarty <pbadari@us.ibm.com> [aik: put XICS_IRQS=1024 instead of 64i, fixed endianness and size] Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
There were a few revisions of the Linux kernel that incorrectly swapped the hcall instructions when they saw ePAPR compliant hypercalls. We already have fixups for those in place when running with PR KVM, but HV KVM and systems that don't implement hypercalls at all are still broken because they fall back to the QEMU implementation of fallback hypercalls. So let's make the fallback hypercall instruction path endian agnostic. This only really works well for 64bit guests, but I don't think there are any 32bit systems left that don't implement real pv hcall support, so we'll never get into this code path. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tristan Gingold 提交于
Remove the code that reduce the result to float32 as the frsqrte instruction is defined to return a double-precision estimate of the reciprocal square root. Although reducing the fractional part is harmless (as the estimation must have at least 12 bits of precision according to the old PEM), reducing the exponent range is not correct. Signed-off-by: NTristan Gingold <gingold@adacore.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Eduardo Habkost 提交于
The kvm-type machine option was left out when MachineState was introduced, preventing the kvm-type option from being used. Add the missing property to the sPAPR machine class, so it can be used. Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Tested-by: NAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Eduardo Habkost 提交于
Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Tested-by: NAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
We tell the guest its page size via AUX vectors. The guest process then uses this page size as information on which boundaries it can mmap() things. However, if the host has a bigger page size granularity than the guest, it can not fulfill these mmap() requests - which falls apart when MAP_FIXED is passed to mmap. So in that case, let the guest know that we're running on a bigger page size granularity than the target would require. This fixes running qemu-ppc (TARGET_PAGE_SIZE=4k) on a 64k page size ppc64 host for me. Signed-off-by: NAlexander Graf <agraf@suse.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Alexey Kardashevskiy 提交于
This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from the H_SET_MODE, for POWER8 (PowerISA 2.07) only. This defines AIL flags for LPCR special register. This changes @excp_prefix according to the mode, takes effect in TCG. This turns support of a new capability PPC2_ISA207S flag for TCG. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
This moves H_SET_MODE_RESOURCE_LE handler to a separate function as there are other "resources" coming and this is going to become ugly. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
This adds DABRX SPR. As DABR(X) are present in POWER CPUs till POWER7 only and POWER8 does not have them (as it implements more powerful facility instead), this limits DABR/DABRX registration by POWER7 (inclusive). Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
This hooks SPR with their "KVM set_one_reg" counterparts which enables their migration. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
POWER8 supports Event-Based Branch Facility (EBB). It is controlled via set of SPRs access to which should generate an "Facility Unavailable" interrupt if the facilities are not enabled in FSCR for problem state. This adds EBB SPRs. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
This adds migration support for registers saved before Transactional Memory (TM) transaction started. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
This adds TM (Transactional Memory) SPRs. This adds generic spr_read_prev_upper32()/spr_write_prev_upper32() to handle upper half SPRs such as TEXASRU which is upper half of TEXASR. Since this is not the only register like that and their numbers go consequently, it makes sense to generalize the helpers. This adds a gen_msr_facility_check() helper which purpose is to generate the Facility Unavailable exception if the facility is disabled. It is a copy of gen_fscr_facility_check() but it checks for enabled facility in MSR rather than FSCR/HFSCR. It still sets the interrupt cause in FSCR/HFSCR (whichever is passed to the helper). This adds spr_read_tm/spr_write_tm/spr_read_tm_upper32/spr_write_tm_upper32 which are used for TM SPRs. This adds TM-relates MSR bits definitions. This enables TM in POWER8 CPU class' msr_mask. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
This adds POWER8 specific PMU MMCR2/MMCRS SPRs. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
This makes user-privileged read/write fail if TAR facility is not enabled in FSCR. Since this is the very first check for enabled in FSCR facility, this also adds gen_fscr_facility_check() for using in spr_write_tar()/ spr_read_tar(). This enables TAR in FSCR for user mode unconditionally. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
This adds an FSCR (Facility Status and Control Register) SPR. This defines names for FSCR bits. This defines new exception type - POWERPC_EXCP_FU - "facility unavailable" (FU). This registers an interrupt vector for it at 0xF60 as PowerISA defines. This adds a TCG helper_fscr_facility_check() helper to raise an exception if the facility is not enabled. It updates the interrupt cause field in FSCR. This adds a TCG translation block generation code. The helper may be used for HFSCR too as it has the same format. The helper raising FU exceptions is not used by this patch but will be in the next ones. This adds gen_update_current_nip() to update NIP in DisasContext. This helper is not used now and will be called before checking for a condition for throwing an FU exception. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
This adds TIR (Thread Identification Register) SPR first defined for server CPUs in PowerISA 2.07. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
This extends init_proc_book3s_64 to support POWER7 and POWER8. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
This replaces gen_spr_7xx() call (which registers 32bit SPRs) with gen_spr_book3s_pmu() call. This removes SPR_7XX_PMC5/6 as they are for 32bit and gen_spr_book3s_pmu() already registers correct PMC5/6 SPRs. This removes explicit MMCRA registration as gen_spr_book3s_pmu() does it anyway. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
This makes use of generic gen_spr_power5p_lpar() which registers LPCR SPR. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
This replaces VRSAVE registration and vscr_init() call with gen_spr_book3s_altivec() which is generic and does the same thing if insns_flags has PPC_ALTIVEC bit set (which POWER7/8 have set). Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
This moves SCFAR/DSCR/CTRL/PPR/PCR PRs to helpers. Later these helpers will be called from generalized init_proc_book3s_64(). This switches init_proc_POWER7() to use generalized gen_spr_book3s_common() which registers CRTL SPR under slightly different names. No change in behaviour or non-debug output is expected. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
This moves TAR SPR to a helper. Later this helper will be called from generalized init_proc_book3s_64(). Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
This moves PIR/PURR/SPURR SPRs to helpers. Later these helpers will be called from generalized init_proc_book3s_64(). Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
This enabled PMU SPRs migration by hooking hypv privileged versions with "KVM one reg" IDs. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
After merging 970s into one class, check_pow_970() is used for all of them. Since POWER5+ is no different in the matter of supported power modes, let's use the same check_pow() callback for POWER5+ too, Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
At the moment every POWER CPU family has its own init_proc_POWERX function. E500 already has common init function so we try to do the same thing. This introduces BOOK3S_CPU_TYPE enum with 2 values - 970 and POWER5+. This introduces generalized init_proc_book3s_64() which accepts a CPU type as a parameter. This uses new init function for 970 and POWER5+ CPU classes. 970 and POWER5+ use the same CPU class initialization except 3 things: 1. logical partitioning is controlled by LPCR (POWER5+) and HID4 (970) SPRs; 2. 970 does not have EAR (External Access Register) SPR and PowerISA 2.03 defines one so keep it only for POWER5+; 3. POWER5+ does not have ALTIVEC so insns_flags does not have PPC_ALTIVEC flag set and gen_spr_book3s_altivec() won't init ALTIVEC for POWER5+. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
Previously LPCR was registered for the 970 class which was wrong as it does not have LPCR. Instead, HID4 is used which this patch registers. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
Compared to PowerISA-compliant CPUs, 970 family has most of them plus PMC7/8 which are only present on 970 but not on POWER5 and later CPUs. Since we are changing SPRs for Book3s/970 families, let's add them too. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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