- 17 8月, 2018 2 次提交
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由 Robert Hoo 提交于
PCONFIG: Platform configuration, enumerated by CPUID.(EAX=07H, ECX=0): EDX[bit18]. Signed-off-by: NRobert Hoo <robert.hu@linux.intel.com> Message-Id: <1530781798-183214-4-git-send-email-robert.hu@linux.intel.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Robert Hoo 提交于
Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as SPEC_CTRL. At present, mark CPUID_7_0_EDX_ARCH_CAPABILITIES unmigratable, per Paolo's comment. Signed-off-by: NRobert Hoo <robert.hu@linux.intel.com> Message-Id: <1530781798-183214-3-git-send-email-robert.hu@linux.intel.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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- 30 7月, 2018 1 次提交
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由 Paolo Bonzini 提交于
MSR_SMI_COUNT started being migrated in QEMU 2.12. Do not migrate it on older machine types, or the subsection causes a load failure for guests that use SMM. Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 23 7月, 2018 1 次提交
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由 Eduardo Habkost 提交于
Rename DCACHE to DATA_CACHE and ICACHE to INSTRUCTION_CACHE. This avoids conflict with Linux asm/cachectl.h macros and fixes build failure on mips hosts. Reported-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Message-Id: <20180717194010.30096-1-ehabkost@redhat.com> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: NAleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: NBabu Moger <babu.moger@amd.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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- 07 7月, 2018 1 次提交
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由 Greg Kurz 提交于
Since commit d6dcc558, '-cpu ?' shows the description of the X86_CPU_TYPE_NAME("max") for the host CPU model: Enables all features supported by the accelerator in the current host instead of the expected: KVM processor with all supported host features or HVF processor with all supported host features This is caused by the early use of kvm_enabled() and hvf_enabled() in a class_init function. Since the accelerator isn't configured yet, both helpers return false unconditionally. A QEMU binary will only be compiled with one of these accelerators, not both. The appropriate description can thus be decided at build time. Signed-off-by: NGreg Kurz <groug@kaod.org> Message-Id: <153055056654.212317.4697363278304826913.stgit@bahia.lan> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 02 7月, 2018 3 次提交
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由 Jan Kiszka 提交于
This implements NPT suport for SVM by hooking into x86_cpu_handle_mmu_fault where it reads the stage-1 page table. Whether we need to perform this 2nd stage translation, and how, is decided during vmrun and stored in hflags2, along with nested_cr3 and nested_pg_mode. As get_hphys performs a direct cpu_vmexit in case of NPT faults, we need retaddr in that function. To avoid changing the signature of cpu_handle_mmu_fault, this passes the value from tlb_fill to get_hphys via the CPU state. This was tested successfully via the Jailhouse hypervisor. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Message-Id: <567473a0-6005-5843-4c73-951f476085ca@web.de> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Philippe Mathieu-Daudé 提交于
Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: NEduardo Habkost <ehabkost@redhat.com> Message-Id: <20180625124238.25339-4-f4bug@amsat.org> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Vitaly Kuznetsov 提交于
Add support for Hyper-V TLB flush which recently got added to KVM. Just like regular Hyper-V we announce HV_EX_PROCESSOR_MASKS_RECOMMENDED regardless of how many vCPUs we have. Windows is 'smart' and uses less expensive non-EX Hypercall whenever possible (when it wants to flush TLB for all vCPUs or the maximum vCPU index in the vCPU set requires flushing is less than 64). Signed-off-by: NVitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20180610184927.19309-1-vkuznets@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 29 6月, 2018 1 次提交
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由 Michael S. Tsirkin 提交于
When guest CPU PM is enabled, and with -cpu host, expose the host CPU MWAIT leaf in the CPUID so guest can make good PM decisions. Note: the result is 100% CPU utilization reported by host as host no longer knows that the CPU is halted. Signed-off-by: NMichael S. Tsirkin <mst@redhat.com> Reviewed-by: NEduardo Habkost <ehabkost@redhat.com> Message-Id: <20180622192148.178309-3-mst@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 23 6月, 2018 11 次提交
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由 Babu Moger 提交于
Remove generic non-intel check while validating hyperthreading support. Certain AMD CPUs can support hyperthreading now. CPU family with TOPOEXT feature can support hyperthreading now. Signed-off-by: NBabu Moger <babu.moger@amd.com> Tested-by: NGeoffrey McRae <geoff@hostfission.com> Reviewed-by: NEduardo Habkost <ehabkost@redhat.com> Message-Id: <1529443919-67509-4-git-send-email-babu.moger@amd.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Babu Moger 提交于
Enable TOPOEXT feature on EPYC CPU. This is required to support hyperthreading on VM guests. Also extend xlevel to 0x8000001E. Disable topoext on PC_COMPAT_2_12 and keep xlevel 0x8000000a. Signed-off-by: NBabu Moger <babu.moger@amd.com> Message-Id: <1529443919-67509-3-git-send-email-babu.moger@amd.com> [ehabkost: Added EPYC-IBPB.xlevel to PC_COMPAT_2_12] Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Babu Moger 提交于
This is part of topoext support. To keep the compatibility, it is better we support all the combination of nr_cores and nr_threads currently supported. By allowing more nr_cores and nr_threads, we might end up with more nodes than we can actually support with the real hardware. We need to fix up the node id to make this work. We can achieve this by shifting the socket_id bits left to address more nodes. Signed-off-by: NBabu Moger <babu.moger@amd.com> Message-Id: <1529443919-67509-2-git-send-email-babu.moger@amd.com> Reviewed-by: NEduardo Habkost <ehabkost@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Konrad Rzeszutek Wilk 提交于
AMD future CPUs expose a mechanism to tell the guest that the Speculative Store Bypass Disable is not needed and that the CPU is all good. This is exposed via the CPUID 8000_0008.EBX[26] bit. See 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf A copy of this document is available at https://bugzilla.kernel.org/show_bug.cgi?id=199889Signed-off-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com> Message-Id: <20180601153809.15259-3-konrad.wilk@oracle.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Konrad Rzeszutek Wilk 提交于
AMD future CPUs expose _two_ ways to utilize the Intel equivalant of the Speculative Store Bypass Disable. The first is via the virtualized VIRT_SPEC CTRL MSR (0xC001_011f) and the second is via the SPEC_CTRL MSR (0x48). The document titled: 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf gives priority of SPEC CTRL MSR over the VIRT SPEC CTRL MSR. A copy of this document is available at https://bugzilla.kernel.org/show_bug.cgi?id=199889 Anyhow, this means that on future AMD CPUs there will be _two_ ways to deal with SSBD. Signed-off-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com> Message-Id: <20180601153809.15259-2-konrad.wilk@oracle.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Eduardo Habkost 提交于
OSPKE is not a static feature flag: it changes dynamically at runtime depending on CR4, and it was never configurable: KVM never returned OSPKE on GET_SUPPORTED_CPUID, and on TCG enables it automatically if CR4_PKE_MASK is set. Remove OSPKE from the feature name array so users don't try to configure it manually. Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Message-Id: <20180611203712.12086-1-ehabkost@redhat.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Eduardo Habkost 提交于
OSXAVE is not a static feature flag: it changes dynamically at runtime depending on CR4, and it was never configurable: KVM never returned OSXSAVE on GET_SUPPORTED_CPUID, and it is not included in TCG_EXT_FEATURES. Remove OSXSAVE from the feature name array so users don't try to configure it manually. Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Message-Id: <20180611203855.13269-1-ehabkost@redhat.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Daniel P. Berrangé 提交于
When using '-cpu help' the list of CPUID features is grouped according to the internal low level CPUID grouping. The data printed results in very long lines too. This combines to make it hard for users to read the output and identify if QEMU knows about the feature they wish to use. This change gets rid of the grouping of features and treats all flags as single list. The list is sorted into alphabetical order and the printing with line wrapping at the 77th column. Signed-off-by: NDaniel P. Berrangé <berrange@redhat.com> Message-Id: <20180606165527.17365-4-berrange@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Daniel P. Berrangé 提交于
The current list of CPU model names output by "-cpu help" is sorted alphabetically based on the internal QOM class name. The text that is displayed, however, uses the CPU model name, which is equivalent to the QOM class name, minus a suffix. Unfortunately that suffix has an effect on the sort ordering, for example, causing the various Broadwell variants to appear reversed: x86 486 x86 Broadwell-IBRS Intel Core Processor (Broadwell, IBRS) x86 Broadwell-noTSX-IBRS Intel Core Processor (Broadwell, no TSX, IBRS x86 Broadwell-noTSX Intel Core Processor (Broadwell, no TSX) x86 Broadwell Intel Core Processor (Broadwell) x86 Conroe Intel Celeron_4x0 (Conroe/Merom Class Core 2) By sorting on the actual CPU model name text that is displayed, the result is x86 486 x86 Broadwell Intel Core Processor (Broadwell) x86 Broadwell-IBRS Intel Core Processor (Broadwell, IBRS) x86 Broadwell-noTSX Intel Core Processor (Broadwell, no TSX) x86 Broadwell-noTSX-IBRS Intel Core Processor (Broadwell, no TSX, IBRS) x86 Conroe Intel Celeron_4x0 (Conroe/Merom Class Core 2) This requires extra string allocations during sorting, but this is not a concern given the usage scenario and the number of CPU models that exist. Signed-off-by: NDaniel P. Berrangé <berrange@redhat.com> Message-Id: <20180606165527.17365-3-berrange@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Daniel P. Berrangé 提交于
Since the addition of the -IBRS CPU model variants, the descriptions shown by '-cpu help' are not well aligned, as several model names overflow the space allowed. Right aligning the CPU model names is also not attractive, because it obscures the common name prefixes of many models. The CPU model name field needs to be 4 characters larger, and be left aligned instead. Signed-off-by: NDaniel P. Berrangé <berrange@redhat.com> Message-Id: <20180606165527.17365-2-berrange@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Babu Moger 提交于
Add support for cpuid leaf CPUID_8000_001E. Build the config that closely match the underlying hardware. Please refer to the Processor Programming Reference (PPR) for AMD Family 17h Model for more details. Signed-off-by: NBabu Moger <babu.moger@amd.com> Message-Id: <1528498581-131037-2-git-send-email-babu.moger@amd.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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- 09 6月, 2018 2 次提交
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由 Babu Moger 提交于
Add information for cpuid 0x8000001D leaf. Populate cache topology information for different cache types (Data Cache, Instruction Cache, L2 and L3) supported by 0x8000001D leaf. Please refer to the Processor Programming Reference (PPR) for AMD Family 17h Model for more details. Signed-off-by: NBabu Moger <babu.moger@amd.com> Message-Id: <1527176614-26271-3-git-send-email-babu.moger@amd.com> Reviewed-by: NEduardo Habkost <ehabkost@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Eduardo Habkost 提交于
Always initialize CPUCaches structs with cache information, even if legacy_cache=true. Use different CPUCaches struct for CPUID[2], CPUID[4], and the AMD CPUID leaves. This will simplify a lot the logic inside cpu_x86_cpuid(). Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Signed-off-by: NBabu Moger <babu.moger@amd.com> Message-Id: <1527176614-26271-2-git-send-email-babu.moger@amd.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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- 23 5月, 2018 1 次提交
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由 Michael S. Tsirkin 提交于
Switch to the header we imported from Linux, this allows us to drop a hack in kvm_i386.h. More code will be dropped in the next patch. Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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- 22 5月, 2018 2 次提交
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由 Konrad Rzeszutek Wilk 提交于
AMD Zen expose the Intel equivalant to Speculative Store Bypass Disable via the 0x80000008_EBX[25] CPUID feature bit. This needs to be exposed to guest OS to allow them to protect against CVE-2018-3639. Signed-off-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com> Reviewed-by: NDaniel P. Berrangé <berrange@redhat.com> Signed-off-by: NDaniel P. Berrangé <berrange@redhat.com> Message-Id: <20180521215424.13520-3-berrange@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Daniel P. Berrangé 提交于
New microcode introduces the "Speculative Store Bypass Disable" CPUID feature bit. This needs to be exposed to guest OS to allow them to protect against CVE-2018-3639. Signed-off-by: NDaniel P. Berrangé <berrange@redhat.com> Reviewed-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com> Signed-off-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com> Message-Id: <20180521215424.13520-2-berrange@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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- 15 5月, 2018 6 次提交
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由 Babu Moger 提交于
The property legacy-cache will be used to control the cache information. If user passes "-cpu legacy-cache" then older information will be displayed even if the hardware supports new information. Otherwise use the statically loaded cache definitions if available. Renamed the previous cache structures to legacy_*. If there is any change in the cache information, then it needs to be initialized in builtin_x86_defs. Signed-off-by: NBabu Moger <babu.moger@amd.com> Tested-by: NGeoffrey McRae <geoff@hostfission.com> Message-Id: <20180514164156.27034-3-babu.moger@amd.com> Reviewed-by: NEduardo Habkost <ehabkost@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Babu Moger 提交于
Initialize pre-determined cache information for EPYC processors. Signed-off-by: NBabu Moger <babu.moger@amd.com> Tested-by: NGeoffrey McRae <geoff@hostfission.com> Message-Id: <20180510204148.11687-5-babu.moger@amd.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Babu Moger 提交于
Add cache information in X86CPUDefinition and CPUX86State. Signed-off-by: NBabu Moger <babu.moger@amd.com> Tested-by: NGeoffrey McRae <geoff@hostfission.com> Reviewed-by: NEduardo Habkost <ehabkost@redhat.com> Message-Id: <20180510204148.11687-3-babu.moger@amd.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Eduardo Habkost 提交于
Instead of having a collection of macros that need to be used in complex expressions to build CPUID data, define a CPUCacheInfo struct that can hold information about a given cache. Helper functions will take a CPUCacheInfo struct as input to encode CPUID leaves for a cache. This will help us ensure consistency between cache information CPUID leaves, and make the existing inconsistencies in CPUID info more visible. Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Signed-off-by: NBabu Moger <babu.moger@amd.com> Tested-by: NGeoffrey McRae <geoff@hostfission.com> Message-Id: <20180510204148.11687-2-babu.moger@amd.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Jingqi Liu 提交于
The CLDEMOTE instruction hints to hardware that the cache line that contains the linear address should be moved("demoted") from the cache(s) closest to the processor core to a level more distant from the processor core. This may accelerate subsequent accesses to the line by other cores in the same coherence domain, especially if the line was written by the core that demotes the line. Intel Snow Ridge has added new cpu feature, CLDEMOTE. The new cpu feature needs to be exposed to guest VM. The bit definition: CPUID.(EAX=7,ECX=0):ECX[bit 25] CLDEMOTE The release document ref below link: https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf Signed-off-by: NJingqi Liu <jingqi.liu@intel.com> Message-Id: <1525406253-54846-1-git-send-email-jingqi.liu@intel.com> Reviewed-by: NEduardo Habkost <ehabkost@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Boqun Feng 提交于
A new cpu model called "KnightsMill" is added to model Knights Mill processors. Compared to "Skylake-Server" cpu model, the following features are added: avx512_4vnniw avx512_4fmaps avx512pf avx512er avx512_vpopcntdq and the following features are removed: pcid invpcid clflushopt avx512dq avx512bw clwb smap rtm mpx xsavec xgetbv1 hle Signed-off-by: NBoqun Feng <boqun.feng@intel.com> Message-Id: <20180320000821.8337-1-boqun.feng@intel.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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- 11 5月, 2018 1 次提交
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由 Vitaly Kuznetsov 提交于
KVM recently gained support for Hyper-V Reenlightenment MSRs which are required to make KVM-on-Hyper-V enable TSC page clocksource to its guests when INVTSC is not passed to it (and it is not passed by default in Qemu as it effectively blocks migration). Signed-off-by: NVitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20180411115036.31832-2-vkuznets@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 17 4月, 2018 1 次提交
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由 Eduardo Habkost 提交于
The assumption in the cpu->max_features code is that anything enabled on GET_SUPPORTED_CPUID should be enabled on "-cpu host". This shouldn't be the case for FEAT_KVM_HINTS. This adds a new FeatureWordInfo::no_autoenable_flags field, that can be used to prevent FEAT_KVM_HINTS bits to be enabled automatically. Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Message-Id: <20180410211534.26079-1-ehabkost@redhat.com> Tested-by: NWanpeng Li <wanpengli@tencent.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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- 09 4月, 2018 1 次提交
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由 Roman Kagan 提交于
In order to guarantee compatibility on migration, QEMU should have complete control over the features it announces to the guest via CPUID. However, the availability of Hyper-V frequency MSRs (HV_X64_MSR_TSC_FREQUENCY and HV_X64_MSR_APIC_FREQUENCY) depends solely on the support for them in the underlying KVM. Introduce "hv-frequencies" cpu property (off by default) which gives QEMU full control over whether these MSRs are announced. While at this, drop the redundant check of the cpu tsc frequency, and decouple this feature from hv-time. Signed-off-by: NRoman Kagan <rkagan@virtuozzo.com> Reviewed-by: NEduardo Habkost <ehabkost@redhat.com> Message-Id: <20180330170209.20627-2-rkagan@virtuozzo.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 20 3月, 2018 3 次提交
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由 Luwei Kang 提交于
Intel processor trace should be disabled when CPUID.(EAX=14H,ECX=0H).ECX.[bit31] is set. Generated packets which contain IP payloads will have LIP values when this bit is set, or IP payloads will have RIP values. Currently, The information of CPUID 14H is constant to make live migration safty and this bit is always 0 in guest even if host support LIP values. Guest sees the bit is 0 will expect IP payloads with RIP values, but the host CPU will generate IP payloads with LIP values if this bit is set in HW. To make sure the value of IP payloads correctly, Intel PT should be disabled when bit[31] is set. Signed-off-by: NLuwei Kang <luwei.kang@intel.com> Message-Id: <1520969191-18162-1-git-send-email-luwei.kang@intel.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Max Reitz 提交于
This patch was generated using the following Coccinelle script: @@ expression Obj; @@ ( - qobject_to_qnum(Obj) + qobject_to(QNum, Obj) | - qobject_to_qstring(Obj) + qobject_to(QString, Obj) | - qobject_to_qdict(Obj) + qobject_to(QDict, Obj) | - qobject_to_qlist(Obj) + qobject_to(QList, Obj) | - qobject_to_qbool(Obj) + qobject_to(QBool, Obj) ) and a bit of manual fix-up for overly long lines and three places in tests/check-qjson.c that Coccinelle did not find. Signed-off-by: NMax Reitz <mreitz@redhat.com> Reviewed-by: NAlberto Garcia <berto@igalia.com> Message-Id: <20180224154033.29559-4-mreitz@redhat.com> Reviewed-by: NEric Blake <eblake@redhat.com> [eblake: swap order from qobject_to(o, X), rebase to master, also a fix to latent false-positive compiler complaint about hw/i386/acpi-build.c] Signed-off-by: NEric Blake <eblake@redhat.com>
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由 Igor Mammedov 提交于
both do nothing as for the first all callers parse_cpu_model() and qmp_query_cpu_model_() should provide non NULL value, so just abort if it's not so. While at it drop cpu_common_class_by_name() which is not need any more as every target has CPUClass::class_by_name callback by now, though abort in case a new arch will forget to define one. Signed-off-by: NIgor Mammedov <imammedo@redhat.com> Message-Id: <1518013857-4372-1-git-send-email-imammedo@redhat.com> Reviewed-by: NEduardo Habkost <ehabkost@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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- 14 3月, 2018 1 次提交
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由 Brijesh Singh 提交于
When SEV is enabled, CPUID 0x8000_001F should provide additional information regarding the feature (such as which page table bit is used to mark the pages as encrypted etc). The details for memory encryption CPUID is available in AMD APM (https://support.amd.com/TechDocs/24594.pdf) Section E.4.17 Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Richard Henderson <rth@twiddle.net> Cc: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: NEduardo Habkost <ehabkost@redhat.com> Signed-off-by: NBrijesh Singh <brijesh.singh@amd.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 13 3月, 2018 2 次提交
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由 Liran Alon 提交于
This MSR returns the number of #SMIs that occurred on CPU since boot. KVM commit 52797bf9a875 ("KVM: x86: Add emulation of MSR_SMI_COUNT") introduced support for emulating this MSR. This commit adds support for QEMU to save/load this MSR for migration purposes. Signed-off-by: NLiran Alon <liran.alon@oracle.com> Reviewed-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com> Signed-off-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Chao Peng 提交于
Expose Intel Processor Trace feature to guest. To make Intel PT live migration safe and get same CPUID information with same CPU model on diffrent host. CPUID[14] is constant in this patch. Intel PT use EPT is first supported in IceLake, the CPUID[14] get on this machine as default value. Intel PT would be disabled if any machine don't support this minial feature list. Signed-off-by: NChao Peng <chao.p.peng@linux.intel.com> Signed-off-by: NLuwei Kang <luwei.kang@intel.com> Message-Id: <1520182116-16485-1-git-send-email-luwei.kang@intel.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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