- 10 12月, 2008 3 次提交
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由 aurel32 提交于
Current implementation of memory-mapped i8042 controller is atm implemented with an interface shift (it_shift) parameter, like most all memory-mapped devices in Qemu. However, this isn't suitable for MIPS Magnum, where i8042 controller is at 0x80005000 up to 0x80005fff. Thomas Bogendoerfer (from #mipslinux) tested the behaviour of a real machine, and found that odd addresses are for status/command register, and even addresses for data register. Attached patch implements this behaviour by replacing the it_shift parameter by a mask one. Incidentally, keyboard now works on OpenBSD 2.3, which accesses i8042 controller at 0x80005060 and 0x80005061. Signed-off-by: NHervé Poussineau <hpoussin@reactos.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5962 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aliguori 提交于
MMIO exits are more expensive in KVM or Xen than in QEMU because they involve, at least, privilege transitions. However, MMIO write operations can be effectively batched if those writes do not have side effects. Good examples of this include VGA pixel operations when in a planar mode. As it turns out, we can get a nice boost in other areas too. Laurent mentioned a 9.7% performance boost in iperf with the coalesced MMIO changes for the e1000 when he originally posted this work for KVM. Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5961 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aliguori 提交于
Prior to kvm-80, memory slot deletion was broken in the KVM kernel modules. In kvm-81, a new capability is introduced to signify that this problem has been fixed. Since we rely on being able to delete memory slots, refuse to work with any kernel module that does not have this capability present. Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5960 c046a42c-6fe2-441c-8c8c-71466251a162
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- 09 12月, 2008 11 次提交
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由 aurel32 提交于
Signed-off-by: NKirill A. Shutemov <kirill@shutemov.name> Acked-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5959 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NKirill A. Shutemov <kirill@shutemov.name> Acked-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5958 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Paul's comment on my first approach to fix the h2g usage in page_find_alloc finally open my eyes about what the code is actually supposed to do: With the help of h2g_valid we can no cleanly check if a freshly allocate page (for host usage) is guest-reachable and, in case it is, mark it reserved in the guest's address range. Signed-off-by: NJan Kiszka <jan.kiszka@web.de> Signed-off-by: NKirill A. Shutemov <kirill@shutemov.name> Acked-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5957 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Introduce h2g_valid to check if a given host address can be converted into a valid guest address. Based on a patch from Jan Kiszka <jan.kiszka@web.de> Signed-off-by: NKirill A. Shutemov <kirill@shutemov.name> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5956 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
h2g can only work on 64-bit hosts if the provided address is mappable to the guest range. Neglecting this was already the source for several bugs. Instrument the macro so that it will trigger earlier in the future (at least as long as we have this kind of mapping mechanism). Based on a patch from Jan Kiszka <jan.kiszka@web.de> Signed-off-by: NKirill A. Shutemov <kirill@shutemov.name> Acked-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5955 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NKirill A. Shutemov <kirill@shutemov.name> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5954 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Remove some ugly outputs with colorgcc Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5953 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5952 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5951 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5950 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Rework the memory load/store: - Unify load/store functions for 32-bit and 64-bit CPU - Don't swap values twice for bit-reverse load/store functions in little endian mode. - On a 64-bit CPU in 32-bit mode, do the address truncation for address computation instead of every load store. Truncate the address when incrementing the address (if needed) - Cache writes to access_types. - Add a few missing calls to gen_set_access_type() Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5949 c046a42c-6fe2-441c-8c8c-71466251a162
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- 08 12月, 2008 26 次提交
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由 balrog 提交于
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5948 c046a42c-6fe2-441c-8c8c-71466251a162
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由 balrog 提交于
Only fix compilation, probably doesn't run. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5947 c046a42c-6fe2-441c-8c8c-71466251a162
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由 balrog 提交于
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5946 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
(Vince Weaver) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5945 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5944 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5943 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Attached patch adds a reset handler to parallel port, so it gets correct register values after a reset. (Hervé Poussineau) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5942 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5941 c046a42c-6fe2-441c-8c8c-71466251a162
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由 malc 提交于
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5940 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
This patch simply implement one register of SH4's SCI := Serial Communication Interface. R2D evaluation board uses SCI for SPI connection. So, Linux kernel for R2D with default configuration causes a QEMU assertion failure when it initializes SPI driver. This patch avoids it and reduces the kernel config modification work for QEMU. Completing SCI implementation task is left. Other board support is desirable to confirm this task, which uses SCI for a serial terminal. (Shin-ichiro KAWASAKI) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5939 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5938 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
SH4 manual say that if a floating point instruction is executed while FD bit in the status register is 1, an exception should be raised. QEMU presently does not do that, so the kernel does not initialize FP state for any thread, nor does it save/restore FP state. The most apparent consequence is that while recent gcc/libc expect double-precision mode to be set by kernel, they run in single-precision mode, and all FP code produces wrong values. This patch fixes this. It also fixes a couple of places where PC was not updated before handling an exception, although both those places deal with invalid instruction and don't lead to any user-visible bugs. (Vladimir Prus) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5937 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
1. hostregs_helper.h: fix comment 2. translate-all.c: rename dyngen_code(_search_pc) to tcg_gen_code(_search_pc) 3. tcg.c: - rename dyngen_table_op_count to tcg_table_op_count - no need to generate a log of dyngen ops generated - rename dyngen_code(_search_pc) to tcg_gen_code(_search_pc) 4. tcg.h: rename dyngen_code(_search_pc) to tcg_gen_code(_search_pc) Signed-off-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5936 c046a42c-6fe2-441c-8c8c-71466251a162
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由 balrog 提交于
Main purpose of this is to delete *physical = address & 0x1fffffff; at target-sh4/helper.c:449, using new mmio rule introduced by #5849 This masking is a nice trick to realize P4/A7 duality of SH registers. But, IMHO, it is logically wrong. Most of SH4 cpu control registers in P4 area(0xfc000000...0xffffffff) have one more address called A7 which is usually P4 address with upper 3bits masked. This is an address only appears in TLB's physical address part. Current code use trick writing drivers as if they are really in A7 (that's why you see many *_A7 in hw/sh*.c), and using translation P4 to A7. Signed-off-by: NTakashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: NAndrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5935 c046a42c-6fe2-441c-8c8c-71466251a162
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由 balrog 提交于
Fixes to be needed for commit #5849 "Change MMIO callbacks..." hw/sh7750.c: - Divide region of CPU control registers to avoid overlapping to peripheral modules. - Delete unused var "icr", which had moved to hw/sh_intc.c. hw/sm501.c: - Merge non page aligned palette registers into the region of control registers. Signed-off-by: NTakashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: NAndrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5934 c046a42c-6fe2-441c-8c8c-71466251a162
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由 blueswir1 提交于
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5933 c046a42c-6fe2-441c-8c8c-71466251a162
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由 balrog 提交于
This patch adds pci support to sh/r2d board. This is the first user of PCIC support I formerly sent. PCIC actually is inside of chip with CPU core on SH7751. But, this code is written as if SH7750 and PCIC are on board. I care little about physical device boundary, but fitting with qemu's design. This patch also adds some BSC (Bus State Controller) registers, because PCI device driver software have to accesses them. Signed-off-by: NTakashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: NAndrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5932 c046a42c-6fe2-441c-8c8c-71466251a162
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由 blueswir1 提交于
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5931 c046a42c-6fe2-441c-8c8c-71466251a162
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由 blueswir1 提交于
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5930 c046a42c-6fe2-441c-8c8c-71466251a162
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由 blueswir1 提交于
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5929 c046a42c-6fe2-441c-8c8c-71466251a162
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由 balrog 提交于
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5928 c046a42c-6fe2-441c-8c8c-71466251a162
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由 balrog 提交于
This patch adds SuperH on-chip PCI controller(PCIC) support. Signed-off-by: NTakashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: NAndrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5927 c046a42c-6fe2-441c-8c8c-71466251a162
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由 balrog 提交于
This adds IRQ controller in FPGA on r2d, and use it for CF. Signed-off-by: NTakashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: NAndrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5926 c046a42c-6fe2-441c-8c8c-71466251a162
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由 balrog 提交于
This patch adds IRL(4bit encoded 15 level interrupt input) support to SH using qemu_irq as a multi level (!=on/off) signal. Signed-off-by: NTakashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: NAndrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5925 c046a42c-6fe2-441c-8c8c-71466251a162
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由 balrog 提交于
This patch adds emulation for a CompactFlash on sh4/r2d board. The device is CF, but wired to be worked as True-IDE mode, and connected directly to SH bus. So, this code is to support generally mmio based IDEs which are supported by "pata_platform" driver in linux kernel. Signed-off-by: NTakashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: NAndrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5924 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5923 c046a42c-6fe2-441c-8c8c-71466251a162
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