1. 05 3月, 2019 21 次提交
  2. 04 3月, 2019 19 次提交
    • P
      Merge remote-tracking branch 'remotes/stefanberger/tags/pull-tpm-2019-02-25-1' into staging · 88687719
      Peter Maydell 提交于
      Merge tpm 2029/02/25 v1
      
      # gpg: Signature made Mon 25 Feb 2019 15:05:12 GMT
      # gpg:                using RSA key 75AD65802A0B4211
      # gpg: Good signature from "Stefan Berger <stefanb@linux.vnet.ibm.com>" [unknown]
      # gpg: WARNING: This key is not certified with a trusted signature!
      # gpg:          There is no indication that the signature belongs to the owner.
      # Primary key fingerprint: B818 B9CA DF90 89C2 D5CE  C66B 75AD 6580 2A0B 4211
      
      * remotes/stefanberger/tags/pull-tpm-2019-02-25-1:
        tpm_tis: convert tpm_tis_show_buffer() to use trace event
        tpm_tis: fix loop that cancels any seizure by a lower locality
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      88687719
    • P
      Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190304' into staging · 1ba530a4
      Peter Maydell 提交于
      s390x updates:
      - tcg: support the floating-point extension facility
      - vfio-ap: support hot(un)plug of vfio-ap device
      - fixes + cleanups
      
      # gpg: Signature made Mon 04 Mar 2019 11:55:39 GMT
      # gpg:                using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF
      # gpg:                issuer "cohuck@redhat.com"
      # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [unknown]
      # gpg:                 aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full]
      # gpg:                 aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full]
      # gpg:                 aka "Cornelia Huck <cohuck@kernel.org>" [unknown]
      # gpg:                 aka "Cornelia Huck <cohuck@redhat.com>" [unknown]
      # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0  18CE DECF 6B93 C6F0 2FAF
      
      * remotes/cohuck/tags/s390x-20190304: (27 commits)
        s390x: Add floating-point extension facility to "qemu" cpu model
        s390x/tcg: Handle all rounding modes overwritten by BFP instructions
        s390x/tcg: Implement rounding mode and XxC for LOAD ROUNDED
        s390x/tcg: Implement XxC and checks for most FP instructions
        s390x/tcg: Prepare for IEEE-inexact-exception control (XxC)
        s390x/tcg: Refactor saving/restoring the bfp rounding mode
        s390x/tcg: Check for exceptions in SET BFP ROUNDING MODE
        s390x/tcg: Handle SET FPC AND LOAD FPC 3-bit BFP rounding modes
        s390x/tcg: Fix simulated-IEEE exceptions
        s390x/tcg: Refactor SET FPC AND SIGNAL handling
        s390x/tcg: Hide IEEE underflows in some scenarios
        s390x/tcg: Fix parts of IEEE exception handling
        s390x/tcg: Factor out conversion of softfloat exceptions
        s390x/tcg: Fix rounding from float128 to uint64_t/uint32_t
        s390x/tcg: Fix TEST DATA CLASS instructions
        s390x/tcg: Implement LOAD COUNT TO BLOCK BOUNDARY
        s390x/tcg: Implement LOAD LENGTHENED short HFP to long HFP
        s390x/tcg: Factor out gen_addi_and_wrap_i64() from get_address()
        s390x/tcg: Factor out vec_full_reg_offset()
        s390x/tcg: Clarify terminology in vec_reg_offset()
        ...
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      1ba530a4
    • P
      Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging · 1d31f187
      Peter Maydell 提交于
      pci, pc, virtio: fixes, cleanups, tests
      
      Lots of work on tests: BiosTablesTest UEFI app,
      vhost-user testing for non-Linux hosts.
      Misc cleanups and fixes all over the place
      Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
      
      # gpg: Signature made Fri 22 Feb 2019 15:51:40 GMT
      # gpg:                using RSA key 281F0DB8D28D5469
      # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
      # gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>" [full]
      # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17  0970 C350 3912 AFBE 8E67
      #      Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA  8A0D 281F 0DB8 D28D 5469
      
      * remotes/mst/tags/for_upstream: (26 commits)
        pci: Sanity test minimum downstream LNKSTA
        hw/smbios: fix offset of type 3 sku field
        pci: Move NVIDIA vendor id to the rest of ids
        virtio-balloon: Safely handle BALLOON_PAGE_SIZE < host page size
        virtio-balloon: Use ram_block_discard_range() instead of raw madvise()
        virtio-balloon: Rework ballon_page() interface
        virtio-balloon: Corrections to address verification
        virtio-balloon: Remove unnecessary MADV_WILLNEED on deflate
        i386/kvm: ignore masked irqs when update msi routes
        contrib/vhost-user-blk: fix the compilation issue
        Revert "contrib/vhost-user-blk: fix the compilation issue"
        pc-dimm: use same mechanism for [get|set]_addr
        tests/data: introduce "uefi-boot-images" with the "bios-tables-test" ISOs
        tests/uefi-test-tools: add build scripts
        tests: introduce "uefi-test-tools" with the BiosTablesTest UEFI app
        roms: build the EfiRom utility from the roms/edk2 submodule
        roms: add the edk2 project as a git submodule
        vhost-user-test: create a temporary directory per TestServer
        vhost-user-test: small changes to init_hugepagefs
        vhost-user-test: create a main loop per TestServer
        ...
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      1d31f187
    • D
      s390x: Add floating-point extension facility to "qemu" cpu model · df192fbc
      David Hildenbrand 提交于
      The floating-point extension facility implemented certain changes to
      BFP, HFP and DFP instructions.
      
      As we don't implement HFP/DFP, we can ignore those completely. Related
      to BFP, the changes include
      - SET BFP ROUNDING MODE (SRNMB) instruction
      - BFP-rounding-mode field in the FPC register is changed to 3 bits
      - CONVERT FROM LOGICAL instructions
      - CONVERT TO LOGICAL instructions
      - Changes (rounding mode + XxC) added to
      -- CONVERT TO FIXED
      -- CONVERT FROM FIXED
      -- LOAD FP INTEGER
      -- LOAD ROUNDED
      -- DIVIDE TO INTEGER
      
      For TCG, we don't implement DIVIDE TO INTEGER, and it is harder to
      implement, so skip that. Also, as we don't implement PFPO, we can skip
      changes to that as well. The other parts are now implemented, we can
      indicate the facility.
      
      z14 PoP mentions that "The floating-point extension facility is installed
      in the z/Architecture architectural mode. When bit 37 is one, bit 42 is
      also one.", meaning that the DFP (decimal-floating-point) facility also
      has to be indicated. We can ignore that for now.
      Signed-off-by: NDavid Hildenbrand <david@redhat.com>
      Message-Id: <20190218122710.23639-16-david@redhat.com>
      Reviewed-by: NThomas Huth <thuth@redhat.com>
      Signed-off-by: NCornelia Huck <cohuck@redhat.com>
      df192fbc
    • D
      s390x/tcg: Handle all rounding modes overwritten by BFP instructions · b12b103e
      David Hildenbrand 提交于
      "round to nearest with ties away from 0" maps to float_round_ties_away.
      "round to prepare for shorter precision" maps to float_round_to_odd.
      
      As all instructions properly check for valid rounding modes in translate.c
      we can add an assert. Fix one missing empty line.
      
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
      Signed-off-by: NDavid Hildenbrand <david@redhat.com>
      Message-Id: <20190218122710.23639-15-david@redhat.com>
      Signed-off-by: NCornelia Huck <cohuck@redhat.com>
      b12b103e
    • D
      s390x/tcg: Implement rounding mode and XxC for LOAD ROUNDED · bdcfcd44
      David Hildenbrand 提交于
      With the floating-point extension facility, LOAD ROUNDED has
      a rounding mode specification and the inexact-exception control (XxC).
      
      Handle them just like e.g. LOAD FP INTEGER.
      Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
      Signed-off-by: NDavid Hildenbrand <david@redhat.com>
      Message-Id: <20190218122710.23639-14-david@redhat.com>
      Signed-off-by: NCornelia Huck <cohuck@redhat.com>
      bdcfcd44
    • D
      s390x/tcg: Implement XxC and checks for most FP instructions · dce0a58f
      David Hildenbrand 提交于
      With the floating-point extension facility
      - CONVERT FROM LOGICAL
      - CONVERT TO LOGICAL
      - CONVERT TO FIXED
      - CONVERT FROM FIXED
      - LOAD FP INTEGER
      have both, a rounding mode specification and the inexact-exception control
      (XxC). Other instructions will be handled separatly.
      
      Check for valid rounding modes and forward also the XxC (via m4). To avoid
      a lot of boilerplate code and changes to the helpers, combine both, the
      m3 and m4 field in a combined 32 bit TCG variable. Perform checks at
      a central place, taking in account if the m3 or m4 field was ignore
      before the floating-point extension facility was introduced.
      Signed-off-by: NDavid Hildenbrand <david@redhat.com>
      Message-Id: <20190218122710.23639-13-david@redhat.com>
      Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
      Signed-off-by: NCornelia Huck <cohuck@redhat.com>
      dce0a58f
    • D
      s390x/tcg: Prepare for IEEE-inexact-exception control (XxC) · cf97f9ff
      David Hildenbrand 提交于
      Some instructions allow to suppress IEEE inexact exceptions.
      
      z14 PoP, 9-23, "Suppression of Certain IEEE Exceptions"
          IEEE-inexact-exception control (XxC): Bit 1 of
          the M4 field is the XxC bit. If XxC is zero, recogni-
          tion of IEEE-inexact exception is not suppressed;
          if XxC is one, recognition of IEEE-inexact excep-
          tion is suppressed.
      
      Especially, handling for overflow/unerflow remains as is, inexact is
      reported along
      
      z14 PoP, 9-23, "Suppression of Certain IEEE Exceptions"
          For example, the IEEE-inexact-exception control (XxC)
          has no effect on the DXC; that is, the DXC for IEEE-
          overflow or IEEE-underflow exceptions along with the
          detail for exact, inexact and truncated, or inexact and
          incremented, is reported according to the actual con-
          dition.
      
      Follow up patches will wire it correctly up for the applicable
      instructions.
      Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
      Signed-off-by: NDavid Hildenbrand <david@redhat.com>
      Message-Id: <20190218122710.23639-12-david@redhat.com>
      Signed-off-by: NCornelia Huck <cohuck@redhat.com>
      cf97f9ff
    • D
      s390x/tcg: Refactor saving/restoring the bfp rounding mode · c0ee7015
      David Hildenbrand 提交于
      We want to reuse this in the context of vector instructions. So use
      better matching names and introduce s390_restore_bfp_rounding_mode().
      
      While at it, add proper newlines.
      Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
      Signed-off-by: NDavid Hildenbrand <david@redhat.com>
      Message-Id: <20190218122710.23639-11-david@redhat.com>
      Signed-off-by: NCornelia Huck <cohuck@redhat.com>
      c0ee7015
    • D
      s390x/tcg: Check for exceptions in SET BFP ROUNDING MODE · b9c737f5
      David Hildenbrand 提交于
      Let's split handling of BFP/DFP rounding mode configuration. Also,
      let's not reuse the sfpc handler, use a separate handler so we can
      properly check for specification exceptions for SRNMB.
      Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
      Signed-off-by: NDavid Hildenbrand <david@redhat.com>
      Message-Id: <20190218122710.23639-10-david@redhat.com>
      Signed-off-by: NCornelia Huck <cohuck@redhat.com>
      b9c737f5
    • D
      s390x/tcg: Handle SET FPC AND LOAD FPC 3-bit BFP rounding modes · 2aea83c6
      David Hildenbrand 提交于
      We already forward the 3 bits correctly in the translation functions. We
      also have to handle them properly and check for specification
      exceptions.
      
      Setting an invalid rounding mode (BFP only, all DFP rounding modes)
      results in a specification exception. Setting unassigned bits in the
      fpc, results in a specification exception.
      
      This fixes LOAD FPC (AND SIGNAL), SET FPC (AND SIGNAL). Also for,
      SET BFP ROUNDING MODE, 3-bit rounding mode is now explicitly checked.
      
      Note: TCG_CALL_NO_WG is required for sfpc handler, as we now inject
      exceptions.
      
      We won't be modeling abscence of the "floating-point extension facility"
      for now, not necessary as most take the facility for granted without
      checking.
      
      z14 PoP, 9-23, "LOAD FPC"
          When the floating-point extension facility is
          installed, bits 29-31 of the second operand must
          specify a valid BFP rounding mode and bits 6-7,
          14-15, 24, and 28 must be zero; otherwise, a
          specification exception is recognized.
      Signed-off-by: NDavid Hildenbrand <david@redhat.com>
      Message-Id: <20190218122710.23639-9-david@redhat.com>
      Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
      Signed-off-by: NCornelia Huck <cohuck@redhat.com>
      2aea83c6
    • D
      s390x/tcg: Fix simulated-IEEE exceptions · 8772bbe4
      David Hildenbrand 提交于
      The trap is triggered based on priority of the enabled signaling flags.
      Only overflow and underflow allow a concurrent inexact exception.
      
      z14 PoP, 9-33, Figure 9-21
      Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
      Signed-off-by: NDavid Hildenbrand <david@redhat.com>
      Message-Id: <20190218122710.23639-8-david@redhat.com>
      Signed-off-by: NCornelia Huck <cohuck@redhat.com>
      8772bbe4
    • D
      s390x/tcg: Refactor SET FPC AND SIGNAL handling · f66a0ecf
      David Hildenbrand 提交于
      We can directly work on the uint64_t value, no need for a temporary
      uint32_t value.
      
      Also cleanup and shorten the comments.
      Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
      Signed-off-by: NDavid Hildenbrand <david@redhat.com>
      Message-Id: <20190218122710.23639-7-david@redhat.com>
      Signed-off-by: NCornelia Huck <cohuck@redhat.com>
      f66a0ecf
    • D
      s390x/tcg: Hide IEEE underflows in some scenarios · 6d6ad1d1
      David Hildenbrand 提交于
      IEEE underflows are not reported when the mask bit is off and we don't
      also have an inexact exception.
      
      z14 PoP, 9-20, "IEEE Underflow":
          An IEEE-underflow exception is recognized for an
          IEEE target when the tininess condition exists and
          either: (1) the IEEE-underflow mask bit in the FPC
          register is zero and the result value is inexact, or (2)
          the IEEE-underflow mask bit in the FPC register is
          one.
      Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
      Signed-off-by: NDavid Hildenbrand <david@redhat.com>
      Message-Id: <20190218122710.23639-6-david@redhat.com>
      Signed-off-by: NCornelia Huck <cohuck@redhat.com>
      6d6ad1d1
    • D
      s390x/tcg: Fix parts of IEEE exception handling · fcb9e9f2
      David Hildenbrand 提交于
      Many things are wrong and some parts cannot be fixed yet. Fix what we
      can fix easily and add two FIXMEs:
      
      The fpc flags are not updated in case an exception is actually injected.
      Inexact exceptions have to be handled separately, as they are the only
      exceptions that can coexist with underflows and overflows.
      
      I reread the horribly complicated chapters in the PoP at least 5 times
      and hope I got it right.
      
      For references:
      - z14 PoP, 9-18, "IEEE Exceptions"
      - z14 PoP, 19-9, Figure 19-8
      Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
      Signed-off-by: NDavid Hildenbrand <david@redhat.com>
      Message-Id: <20190218122710.23639-5-david@redhat.com>
      Signed-off-by: NCornelia Huck <cohuck@redhat.com>
      fcb9e9f2
    • D
      s390x/tcg: Factor out conversion of softfloat exceptions · 4b70fc54
      David Hildenbrand 提交于
      We want to reuse that function in vector instruction context. While at it,
      cleanup the code, using defines for magic values and avoiding the
      handcrafted bit conversion.
      Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
      Signed-off-by: NDavid Hildenbrand <david@redhat.com>
      Message-Id: <20190218122710.23639-4-david@redhat.com>
      Signed-off-by: NCornelia Huck <cohuck@redhat.com>
      4b70fc54
    • D
      s390x/tcg: Fix rounding from float128 to uint64_t/uint32_t · 3af471f9
      David Hildenbrand 提交于
      Let's use the proper conversion functions now that we have them.
      Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
      Signed-off-by: NDavid Hildenbrand <david@redhat.com>
      Message-Id: <20190218122710.23639-3-david@redhat.com>
      Signed-off-by: NCornelia Huck <cohuck@redhat.com>
      3af471f9
    • D
      s390x/tcg: Fix TEST DATA CLASS instructions · fc7cc951
      David Hildenbrand 提交于
      Let's detect normal and denormal ("subnormal") numbers reliably. Also
      test for quiet NaN's. As only one class is possible, test common cases
      first.
      
      While at it, use a better check to test for the mask bits in the data
      class mask. The data class mask has 12 bits, whereby bit 0 is the
      leftmost bit and bit 11 the rightmost bit. In the PoP an easy to read
      table with the numbers is provided for the VECTOR FP TEST DATA CLASS
      IMMEDIATE instruction, the table for TEST DATA CLASS is more confusing
      as it is based on 64 bit values.
      
      Factor the checks out into separate functions, as they will also be
      needed for floating point vector instructions. We can use a makro to
      generate the functions.
      Signed-off-by: NDavid Hildenbrand <david@redhat.com>
      Message-Id: <20190218122710.23639-2-david@redhat.com>
      Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
      Signed-off-by: NCornelia Huck <cohuck@redhat.com>
      fc7cc951
    • D
      s390x/tcg: Implement LOAD COUNT TO BLOCK BOUNDARY · 6d930332
      David Hildenbrand 提交于
      Use a new CC helper to calculate the CC lazily if needed. While the
      PoP mentions that "A 32-bit unsigned binary integer" is placed into the
      first operand, there is no word telling that the other 32 bits (high
      part) are left untouched. Maybe the other 32-bit are unpredictable.
      So store 64 bit for now.
      
      Bit magic courtesy of Richard.
      Signed-off-by: NDavid Hildenbrand <david@redhat.com>
      Message-Id: <20190225200318.16102-8-david@redhat.com>
      Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
      Signed-off-by: NCornelia Huck <cohuck@redhat.com>
      6d930332