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  1. 13 3月, 2019 17 次提交
  3. 12 3月, 2019 23 次提交
    • P
      Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging · 2cb73afa
      由 Peter Maydell 提交于 
      Machine queue, 2019-03-11

* memfd fixes (Ilya Maximets)
* Move nvdimms state into struct MachineState (Eric Auger)
* hostmem-file: reject invalid pmem file sizes (Stefan Hajnoczi)

# gpg: Signature made Tue 12 Mar 2019 00:57:41 GMT
# gpg:                using RSA key 2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full]
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/machine-next-pull-request:
  memfd: improve error messages
  memfd: set up correct errno if not supported
  memfd: always check for MFD_CLOEXEC
  hostmem-memfd: disable for systems without sealing support
  machine: Move nvdimms state into struct MachineState
  nvdimm: Rename AcpiNVDIMMState into NVDIMMState
  hostmem-file: reject invalid pmem file sizes
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      2cb73afa
    • P
      Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20190311.0' into staging · 46316f1d
      由 Peter Maydell 提交于 
      VFIO updates 2019-03-11

 - Resolution support for mdev displays supporting EDID interface
   (Gerd Hoffmann)

# gpg: Signature made Mon 11 Mar 2019 19:17:39 GMT
# gpg:                using RSA key 239B9B6E3BB08B22
# gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>" [full]
# gpg:                 aka "Alex Williamson <alex@shazbot.org>" [full]
# gpg:                 aka "Alex Williamson <alwillia@redhat.com>" [full]
# gpg:                 aka "Alex Williamson <alex.l.williamson@gmail.com>" [full]
# Primary key fingerprint: 42F6 C04E 540B D1A9 9E7B  8A90 239B 9B6E 3BB0 8B22

* remotes/awilliam/tags/vfio-updates-20190311.0:
  vfio/display: delay link up event
  vfio/display: add xres + yres properties
  vfio/display: add edid support.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      46316f1d
    • P
      Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-pull-request' into staging · a6d3c238
      由 Peter Maydell 提交于 
      fw_cfg and thunk code clean up

# gpg: Signature made Mon 11 Mar 2019 19:11:03 GMT
# gpg:                using RSA key F30C38BD3F2FBE3C
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg:                 aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* remotes/vivier2/tags/trivial-branch-pull-request:
  hw/nvram/fw_cfg: Use the ldst API
  hw/arm/virt: Remove null-check in virt_build_smbios()
  hw/i386: Remove unused include
  hw/nvram/fw_cfg: Remove the unnecessary boot_splash_filedata_size
  thunk: improve readability of allocation loop
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      a6d3c238
    • P
      Merge remote-tracking branch 'remotes/armbru/tags/pull-pflash-2019-03-11' into staging · eda1df03
      由 Peter Maydell 提交于 
      Pflash and firmware configuration patches for 2019-03-11

# gpg: Signature made Mon 11 Mar 2019 21:59:12 GMT
# gpg:                using RSA key 3870B400EB918653
# gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full]
# gpg:                 aka "Markus Armbruster <armbru@pond.sub.org>" [full]
# Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867  4E5F 3870 B400 EB91 8653

* remotes/armbru/tags/pull-pflash-2019-03-11: (27 commits)
  docs/interop/firmware.json: Prefer -machine to if=pflash
  pc: Support firmware configuration with -blockdev
  pc_sysfw: Pass PCMachineState to pc_system_firmware_init()
  pc_sysfw: Remove unused PcSysFwDevice
  pflash_cfi01: Add pflash_cfi01_get_blk() helper
  vl: Create block backends before setting machine properties
  vl: Factor configure_blockdev() out of main()
  vl: Improve legibility of BlockdevOptions queue
  sysbus: Fix latent bug with onboard devices
  vl: Fix latent bug with -global and onboard devices
  qom: Move compat_props machinery from qdev to QOM
  qdev: Fix latent bug with compat_props and onboard devices
  pflash: Clean up after commit 368a354f, part 2
  pflash: Clean up after commit 368a354f, part 1
  mips_malta: Clean up definition of flash memory size somewhat
  hw/mips/malta: Restrict 'bios_size' variable scope
  hw/mips/malta: Remove fl_sectors variable
  mips_malta: Delete disabled, broken DEBUG_BOARD_INIT code
  r2d: Fix flash memory size, sector size, width, device ID
  ppc405_boards: Don't size flash memory to match backing image
  ...
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      eda1df03
    • P
      Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.0-20190312' into staging · bc76b714
      由 Peter Maydell 提交于 
      ppc patch queue for 2019-03-10

This pull requests supersedes ppc-for-4.0-20190310.  Changes are:
 * Fixed a bunch of minor style problems
 * Suppressed warnings about Spectre/Meltdown mitigations with TCG
 * Added one more patch, a preliminary fix towards the not-quite-ready
   support for NVLink VFIO passthrough.

This is a final pull request before the 4.0 soft freeze.  Changes
include:
  * A Great Renaming to use camel case properly in spapr code
  * Optimization of some vector instructions
  * Support for POWER9 cpus in the powernv machine
  * Fixes a regression from the last pull request in handling VSX
    instructions with mixed operands from the FPR and VMX parts of the
    register array
  * Optimization hack to avoid scanning all the (empty) entries on a
    new IOMMU window
  * Add FSL I2C controller model for E500
  * Support for KVM acceleration of the H_PAGE_INIT hypercall on spapr
  * Update u-boot image for E500
  * Enable Specre/Meltdown mitigations by default on the new machine type
  * Enable large decrementer support for POWER9

# gpg: Signature made Tue 12 Mar 2019 08:14:51 GMT
# gpg:                using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full]
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full]
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full]
# gpg:                 aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-4.0-20190312: (62 commits)
  vfio: Make vfio_get_region_info_cap public
  Suppress test warnings about missing Spectre/Meltdown mitigations with TCG
  spapr: Use CamelCase properly
  target/ppc: Optimize x[sv]xsigdp using deposit_i64()
  target/ppc: Optimize xviexpdp() using deposit_i64()
  target/ppc: add HV support for POWER9
  ppc/pnv: add a "ibm,opal/power-mgt" device tree node on POWER9
  ppc/pnv: add more dummy XSCOM addresses
  ppc/pnv: activate XSCOM tests for POWER9
  ppc/pnv: POWER9 XSCOM quad support
  ppc/pnv: extend XSCOM core support for POWER9
  ppc/pnv: add a OCC model for POWER9
  ppc/pnv: add a OCC model class
  ppc/pnv: add SerIRQ routing registers
  ppc/pnv: add a LPC Controller model for POWER9
  ppc/pnv: add a 'dt_isa_nodename' to the chip
  ppc/pnv: add a LPC Controller class model
  ppc/pnv: lpc: fix OPB address ranges
  ppc/pnv: add a PSI bridge model for POWER9
  ppc/pnv: add a PSI bridge class model
  ...
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      bc76b714
    • A
      vfio: Make vfio_get_region_info_cap public · 013002f0
      由 Alexey Kardashevskiy 提交于 
      This makes vfio_get_region_info_cap() to be used in quirks.
Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru>
Acked-by: NAlex Williamson <alex.williamson@redhat.com>
Message-Id: <20190307050518.64968-3-aik@ozlabs.ru>
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      013002f0
    • D
      Suppress test warnings about missing Spectre/Meltdown mitigations with TCG · ba3b40de
      由 David Gibson 提交于 
      The new pseries-4.0 machine type defaults to enabling Spectre/Meltdown
mitigations.  Unfortunately those mitigations aren't implemented for TCG
because we're not yet sure if they're necessary or how to implement them.
We don't fail fatally, but we do warn in this case, because it is quite
plausible that Spectre/Meltdown can be exploited through TCG (at least for
the guest to get access to the qemu address space).

This create noise in our testcases though.  So, modify the affected tests
to explicitly disable the mitigations to suppress these warnings.
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      ba3b40de
    • D
      spapr: Use CamelCase properly · ce2918cb
      由 David Gibson 提交于 
      The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of.  There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".

That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.

In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words".  So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.

In addition to case changes, we also make some other identifier renames:
  VIOsPAPR* -> SpaprVio*
    The reverse word ordering was only ever used to mitigate the capital
    cluster, so revert to the natural ordering.
  VIOsPAPRVTYDevice -> SpaprVioVty
  VIOsPAPRVLANDevice -> SpaprVioVlan
    Brevity, since the "Device" didn't add useful information
  sPAPRDRConnector -> SpaprDrc
  sPAPRDRConnectorClass -> SpaprDrcClass
    Brevity, and makes it clearer this is the same thing as a "DRC"
    mentioned in many other places in the code

This is 100% a mechanical search-and-replace patch.  It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      ce2918cb
    • P
      target/ppc: Optimize x[sv]xsigdp using deposit_i64() · dd977e4f
      由 Philippe Mathieu-Daudé 提交于 
      Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20190309214255.9952-3-f4bug@amsat.org>
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      dd977e4f
    • P
      target/ppc: Optimize xviexpdp() using deposit_i64() · cde0a41c
      由 Philippe Mathieu-Daudé 提交于 
      The t0 tcg_temp register is now unused, remove it.
Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20190309214255.9952-2-f4bug@amsat.org>
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      cde0a41c
    • C
      target/ppc: add HV support for POWER9 · da874d90
      由 Cédric Le Goater 提交于 
      We now have enough support to boot a PowerNV machine with a POWER9
processor. Allow HV mode on POWER9.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Message-Id: <20190307223548.20516-16-clg@kaod.org>
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      da874d90
    • C
      ppc/pnv: add a "ibm,opal/power-mgt" device tree node on POWER9 · e5694793
      由 Cédric Le Goater 提交于 
      Activate only stop0 and stop1 levels. We should not need more levels
when under QEMU.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Message-Id: <20190307223548.20516-15-clg@kaod.org>
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      e5694793
    • C
      ppc/pnv: add more dummy XSCOM addresses · bc565116
      由 Cédric Le Goater 提交于 
      To improve OPAL/skiboot support. We don't need to strictly model these
XSCOM accesses.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Message-Id: <20190307223548.20516-14-clg@kaod.org>
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      bc565116
    • C
      ppc/pnv: activate XSCOM tests for POWER9 · e5a0c52a
      由 Cédric Le Goater 提交于 
      We now have enough support to let the XSCOM test run on POWER9.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Message-Id: <20190307223548.20516-13-clg@kaod.org>
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      e5a0c52a
    • C
      ppc/pnv: POWER9 XSCOM quad support · 5dad902c
      由 Cédric Le Goater 提交于 
      The POWER9 processor does not support per-core frequency control. The
cores are arranged in groups of four, along with their respective L2
and L3 caches, into a structure known as a Quad. The frequency must be
managed at the Quad level.

Provide a basic Quad model to fake the settings done by the firmware
on the Non-Cacheable Unit (NCU). Each core pair (EX) needs a special
BAR setting for the TIMA area of XIVE because it resides on the same
address on all chips.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Message-Id: <20190307223548.20516-12-clg@kaod.org>
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      5dad902c
    • C
      ppc/pnv: extend XSCOM core support for POWER9 · 90ef386c
      由 Cédric Le Goater 提交于 
      Provide a new class attribute to define XSCOM operations per CPU
family and add a couple of XSCOM addresses controlling the power
management states of the core on POWER9.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Message-Id: <20190307223548.20516-11-clg@kaod.org>
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      90ef386c
    • C
      ppc/pnv: add a OCC model for POWER9 · 6598a70d
      由 Cédric Le Goater 提交于 
      The OCC on POWER9 is very similar to the one found on POWER8. Provide
the same routines with P9 values for the registers and IRQ number.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Message-Id: <20190307223548.20516-10-clg@kaod.org>
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      6598a70d
    • C
      ppc/pnv: add a OCC model class · 3233838c
      由 Cédric Le Goater 提交于 
      To ease the introduction of the OCC model for POWER9, provide a new
class attributes to define XSCOM operations per CPU family and a PSI
IRQ number.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au>
Message-Id: <20190307223548.20516-9-clg@kaod.org>
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      3233838c
    • C
      ppc/pnv: add SerIRQ routing registers · 8207b906
      由 Cédric Le Goater 提交于 
      This is just a simple reminder that SerIRQ routing should be
addressed.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Message-Id: <20190307223548.20516-8-clg@kaod.org>
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      8207b906
    • C
      ppc/pnv: add a LPC Controller model for POWER9 · 15376c66
      由 Cédric Le Goater 提交于 
      The LPC Controller on POWER9 is very similar to the one found on
POWER8 but accesses are now done via on MMIOs, without the XSCOM and
ECCB logic. The device tree is populated differently so we add a
specific POWER9 routine for the purpose.

SerIRQ routing is yet to be done.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Message-Id: <20190307223548.20516-7-clg@kaod.org>
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      15376c66
    • C
      ppc/pnv: add a 'dt_isa_nodename' to the chip · 64d011d5
      由 Cédric Le Goater 提交于 
      The ISA bus has a different DT nodename on POWER9. Compute the name
when the PnvChip is realized, that is before it is used by the machine
to populate the device tree with the ISA devices.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Message-Id: <20190307223548.20516-6-clg@kaod.org>
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      64d011d5
    • C
      ppc/pnv: add a LPC Controller class model · 82514be2
      由 Cédric Le Goater 提交于 
      It will ease the introduction of the LPC Controller model for POWER9.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au>
Message-Id: <20190307223548.20516-5-clg@kaod.org>
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      82514be2
    • C
      ppc/pnv: lpc: fix OPB address ranges · 6f89f48e
      由 Cédric Le Goater 提交于 
      The PowerNV LPC Controller exposes different sets of registers for
each of the functional units it encompasses, among which the OPB
(On-Chip Peripheral Bus) Master and Arbitrer and the LPC HOST
Controller.

The mapping addresses of each register range are correct but the sizes
are too large. Fix the sizes and define the OPB Arbitrer range to fill
the gap between the OPB Master registers and the LPC HOST Controller
registers.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Message-Id: <20190307223548.20516-4-clg@kaod.org>
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      6f89f48e