- 24 3月, 2016 11 次提交
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由 Cédric Le Goater 提交于
commit fce55481360d "ppc: A couple more dummy POWER8 Book4 regs" squashed in to rapidly a set of POWER8 Book4 regs in the wrong routine. This patch introduces the missing gen_spr_power8_book4() routine to fix their location. Signed-off-by: NCédric Le Goater <clg@fr.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Benjamin Herrenschmidt 提交于
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> [clg: squashed in patch 'ppc: Add dummy ACOP SPR' ] Signed-off-by: NCédric Le Goater <clg@fr.ibm.com> Reviewed-by: NThomas Huth <thuth@redhat.com> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Benjamin Herrenschmidt 提交于
We should implement HW breakpoint/watchpoint, qemu supports them... Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: NThomas Huth <thuth@redhat.com> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Benjamin Herrenschmidt 提交于
With appropriate AMR-like masks. Not actually used by the translation logic at that point Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> [clg: changed spr_register_hv(SPR_IAMR) to spr_register_kvm_hv(SPR_IAMR) changed gen_spr_amr() prototype ] Signed-off-by: NCédric Le Goater <clg@fr.ibm.com> Reviewed-by: NThomas Huth <thuth@redhat.com> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Benjamin Herrenschmidt 提交于
The masks weren't chosen nor applied properly. The architecture specifies that writes to AMR are masked by UAMOR for PR=1, otherwise AMOR for HV=0. The writes to UAMOR are masked by AMOR for HV=0 Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> [clg: moved gen_spr_amr() prototype change to next patch ] Signed-off-by: NCédric Le Goater <clg@fr.ibm.com> Reviewed-by: NThomas Huth <thuth@redhat.com> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Benjamin Herrenschmidt 提交于
Make sure we give the guest full authorization Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: NThomas Huth <thuth@redhat.com> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Benjamin Herrenschmidt 提交于
It's supposed to be an instruction counter. For now make us not crash when accessing it. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: NThomas Huth <thuth@redhat.com> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Benjamin Herrenschmidt 提交于
And move the code adjusting the MSR mask and calling kvmppc_set_papr() to it. This allows us to add a few more things such as disabling setting of MSR:HV and appropriate LPCR bits which will be used when fixing the exception model. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> [clg: removed LPCR setting ] Signed-off-by: NCédric Le Goater <clg@fr.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Benjamin Herrenschmidt 提交于
We don't give them a KVM reg number to most of the registers yet as no current KVM version supports HV mode. For DAWR and DAWRX, the KVM reg number is needed since this register can be set by the guest via the H_SET_MODE hypercall. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> [clg: squashed in patch 'ppc: Add KVM numbers to some P8 SPRs' changed the commit log with a proposal of Thomas Huth removed all hunks except those related to AMOR and DAWR* ] Signed-off-by: NCédric Le Goater <clg@fr.ibm.com> Reviewed-by: NThomas Huth <thuth@redhat.com> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Benjamin Herrenschmidt 提交于
The current set of spr_register_* macros only take the user and supervisor function pointers. To make the transition easy, we don't change that but we add "_hv" variants that can be used to register all 3 sets. To simplify the transition, users of the "old" macro will set the hypervisor callback to be the same as the supervisor one. The new registration function only needs to be used for registers that are either hypervisor only or behave differently in HV mode. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> [clg: fixed else if condition in gen_op_mfspr() ] Signed-off-by: NCédric Le Goater <clg@fr.ibm.com> Reviewed-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Laurent Vivier 提交于
When a qemu-system-ppc64 is started, the 64-bit mode bit is not set in MSR. Signed-off-by: NLaurent Vivier <lvivier@redhat.com> Reviewed-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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- 16 3月, 2016 4 次提交
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由 Alexey Kardashevskiy 提交于
This adds a new POWER8+NVLink CPU PVR which core is identical to POWER8 but has a different PVR. The only available machine now has PVR pvr 004c 0100 so this defines "POWER8NVL" alias as v1.0. The corresponding kernel commit is https://github.com/torvalds/linux/commit/ddee09c099c3 "powerpc: Add PVR for POWER8NVL processor" Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Benjamin Herrenschmidt 提交于
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Thomas Huth 提交于
The TAR special purpose register currently does not get migrated under KVM because it does not get synchronized with the kernel. Use spr_register_kvm() instead of spr_register() to fix this issue. Signed-off-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Thomas Huth 提交于
POWER8 / PowerISA 2.07 has a new special purpose register called PSPB ("Problem State Priority Boost Register"). The contents of this register are currently lost during migration. To be able to migrate this register, too, we've got to define this SPR along with the other SPRs of POWER8. Signed-off-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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- 09 2月, 2016 2 次提交
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由 Eric Blake 提交于
Similar to the previous patch, it's nice to have all functions in the tree that involve a visitor and a name for conversion to or from QAPI to consistently stick the 'name' parameter next to the Visitor parameter. Done by manually changing include/qom/object.h and qom/object.c, then running this Coccinelle script and touching up the fallout (Coccinelle insisted on adding some trailing whitespace). @ rule1 @ identifier fn; typedef Object, Visitor, Error; identifier obj, v, opaque, name, errp; @@ void fn - (Object *obj, Visitor *v, void *opaque, const char *name, + (Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { ... } @@ identifier rule1.fn; expression obj, v, opaque, name, errp; @@ fn(obj, v, - opaque, name, + name, opaque, errp) Signed-off-by: NEric Blake <eblake@redhat.com> Reviewed-by: NMarc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <1454075341-13658-20-git-send-email-eblake@redhat.com> Signed-off-by: NMarkus Armbruster <armbru@redhat.com>
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由 Eric Blake 提交于
JSON uses "name":value, but many of our visitor interfaces were called with visit_type_FOO(v, &value, name, errp). This can be a bit confusing to have to mentally swap the parameter order to match JSON order. It's particularly bad for visit_start_struct(), where the 'name' parameter is smack in the middle of the otherwise-related group of 'obj, kind, size' parameters! It's time to do a global swap of the parameter ordering, so that the 'name' parameter is always immediately after the Visitor argument. Additional reason in favor of the swap: the existing include/qjson.h prefers listing 'name' first in json_prop_*(), and I have plans to unify that file with the qapi visitors; listing 'name' first in qapi will minimize churn to the (admittedly few) qjson.h clients. Later patches will then fix docs, object.h, visitor-impl.h, and those clients to match. Done by first patching scripts/qapi*.py by hand to make generated files do what I want, then by running the following Coccinelle script to affect the rest of the code base: $ spatch --sp-file script `git grep -l '\bvisit_' -- '**/*.[ch]'` I then had to apply some touchups (Coccinelle insisted on TAB indentation in visitor.h, and botched the signature of visit_type_enum() by rewriting 'const char *const strings[]' to the syntactically invalid 'const char*const[] strings'). The movement of parameters is sufficient to provoke compiler errors if any callers were missed. // Part 1: Swap declaration order @@ type TV, TErr, TObj, T1, T2; identifier OBJ, ARG1, ARG2; @@ void visit_start_struct -(TV v, TObj OBJ, T1 ARG1, const char *name, T2 ARG2, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp) { ... } @@ type bool, TV, T1; identifier ARG1; @@ bool visit_optional -(TV v, T1 ARG1, const char *name) +(TV v, const char *name, T1 ARG1) { ... } @@ type TV, TErr, TObj, T1; identifier OBJ, ARG1; @@ void visit_get_next_type -(TV v, TObj OBJ, T1 ARG1, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, TErr errp) { ... } @@ type TV, TErr, TObj, T1, T2; identifier OBJ, ARG1, ARG2; @@ void visit_type_enum -(TV v, TObj OBJ, T1 ARG1, T2 ARG2, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp) { ... } @@ type TV, TErr, TObj; identifier OBJ; identifier VISIT_TYPE =~ "^visit_type_"; @@ void VISIT_TYPE -(TV v, TObj OBJ, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, TErr errp) { ... } // Part 2: swap caller order @@ expression V, NAME, OBJ, ARG1, ARG2, ERR; identifier VISIT_TYPE =~ "^visit_type_"; @@ ( -visit_start_struct(V, OBJ, ARG1, NAME, ARG2, ERR) +visit_start_struct(V, NAME, OBJ, ARG1, ARG2, ERR) | -visit_optional(V, ARG1, NAME) +visit_optional(V, NAME, ARG1) | -visit_get_next_type(V, OBJ, ARG1, NAME, ERR) +visit_get_next_type(V, NAME, OBJ, ARG1, ERR) | -visit_type_enum(V, OBJ, ARG1, ARG2, NAME, ERR) +visit_type_enum(V, NAME, OBJ, ARG1, ARG2, ERR) | -VISIT_TYPE(V, OBJ, NAME, ERR) +VISIT_TYPE(V, NAME, OBJ, ERR) ) Signed-off-by: NEric Blake <eblake@redhat.com> Reviewed-by: NMarc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <1454075341-13658-19-git-send-email-eblake@redhat.com> Signed-off-by: NMarkus Armbruster <armbru@redhat.com>
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- 30 1月, 2016 7 次提交
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由 David Gibson 提交于
Now that the TCG and spapr code has been extended to allow (semi-) arbitrary page encodings in the CPU's 'sps' table, we can add the many page sizes supported by real POWER7 and POWER8 hardware that we previously didn't support in TCG. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: NAlexander Graf <agraf@suse.de>
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由 Anton Blanchard 提交于
Add the XML and functions to get and set VSX registers. Signed-off-by: NAnton Blanchard <anton@samba.org> (fixed little-endian guests) Signed-off-by: NGreg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Greg Kurz 提交于
Let's reuse the ppc_maybe_bswap_register() helper, like we already do with the general registers. Signed-off-by: NGreg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Greg Kurz 提交于
Altivec registers are 128-bit wide. They are stored in memory as two 64-bit values that must be byteswapped when the guest is little-endian. Let's reuse the ppc_maybe_bswap_register() helper for this. We also need to fix the ordering of the 64-bit elements according to the target endianness, for both system and user mode. Signed-off-by: NGreg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Greg Kurz 提交于
This helper will be used to support Altivec registers in little-endian guests. This patch does not change functionnality. Note: I had to put the helper some lines away from the gdb_*_avr_reg() routines to get a more readable patch. Signed-off-by: NGreg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Greg Kurz 提交于
Let's reuse the ppc_maybe_bswap_register() helper, like we already do with the general registers. Signed-off-by: NGreg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 David Gibson 提交于
Current ppc_set_compat() returns -1 for errors, and also (unconditionally) reports an error message. The caller in h_client_architecture_support() may then report it again using an outdated fprintf(). Clean this up by using the modern error reporting mechanisms. Also add strerror(errno) to the error message. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NThomas Huth <thuth@redhat.com> Reviewed-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NMarkus Armbruster <armbru@redhat.com>
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- 29 1月, 2016 1 次提交
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由 Peter Maydell 提交于
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1453832250-766-6-git-send-email-peter.maydell@linaro.org
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- 27 1月, 2016 1 次提交
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由 David Hildenbrand 提交于
This patch provides the name of the architecture in the target.xml if available. This allows the remote gdb to detect the target architecture on its own - so there is no need to specify it manually (e.g. if gdb is started without a binary) using "set arch *arch_name*". The name of the architecture is provided by a callback that can be implemented by all architectures. The arm implementation has special handling for iwmmxt and returns arm otherwise. This can be extended if necessary. Signed-off-by: NDavid Hildenbrand <dahi@linux.vnet.ibm.com> Acked-by: NCornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: NChristian Borntraeger <borntraeger@de.ibm.com> [rework to use a callback] Message-Id: <1449144881-130935-1-git-send-email-borntraeger@de.ibm.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NCornelia Huck <cornelia.huck@de.ibm.com>
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- 15 1月, 2016 1 次提交
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由 Andrew Jones 提交于
Only one of three architectures implementing qmp-dump-guest-memory write qemu notes. And, another architecture (arm/aarch64) is coming, which won't use them either. Make the common implementation truly common. (No functional change.) Signed-off-by: NAndrew Jones <drjones@redhat.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1452542185-10914-3-git-send-email-drjones@redhat.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 06 11月, 2015 1 次提交
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由 Julio Guerra 提交于
Fix the index used to read the IBAT's vector which results in IBAT0..3 instead of IBAT4..N. The bug appeared by saving/restoring contexts including IBATs values. Signed-off-by: NJulio Guerra <julio@farjump.io> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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- 23 10月, 2015 2 次提交
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由 Benjamin Herrenschmidt 提交于
LoPAPR defines a "ibm,pa-features" per-CPU device tree property which describes extended features of the Processor Architecture. This adds the property to the device tree. At the moment this is the copy of what pHyp advertises except "I=1 (cache inhibited) Large Pages" which is enabled for TCG and disabled when running under HV KVM host with 4K system page size. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> [aik: rebased, changed commit log, moved ci_large_pages initialization, renamed pa_features arrays] Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Benjamin Herrenschmidt 提交于
This removes unused POWERPC_MMU_2_06a/POWERPC_MMU_2_06d. This replaces POWERPC_MMU_64B with POWERPC_MMU_2_03 for POWER5+ to be more explicit about the version of the PowerISA supported. This defines POWERPC_MMU_2_07 and uses it for the POWER8 CPU family. This will not have an immediate effect now but it will in the following patch. This should cause no behavioural change. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> [aik: rebased, changed commit log] Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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- 11 9月, 2015 1 次提交
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由 Shraddha Barke 提交于
Compress lines and remove the variable ret. Change made using Coccinelle script @@ expression ret; @@ - if (ret) return ret; - return 0; + return ret; @@ local idexpression ret; expression e; @@ - ret = e; - return ret; + return e; @@ type T; identifier i; @@ - T i; ... when != i Signed-off-by: NShraddha Barke <shraddha.6596@gmail.com> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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- 09 7月, 2015 3 次提交
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由 Peter Crosthwaite 提交于
The callers (most of them in target-foo/cpu.c) to this function all have the cpu pointer handy. Just pass it to avoid an ENV_GET_CPU() from core code (in exec.c). Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Richard Henderson <rth@twiddle.net> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Michael Walle <michael@walle.cc> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Anthony Green <green@moxielogic.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: NAndreas Färber <afaerber@suse.de> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: NAndreas Färber <afaerber@suse.de>
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由 Bharata B Rao 提交于
Move cpu_exec_init() call from instance_init to realize. This allows any failures from cpu_exec_init() to be handled appropriately. Also add corresponding cpu_exec_exit() call from unrealize. cpu_dt_id assignment from instance_init is no longer needed since correct assignment for cpu_dt_id is already present in realizefn. Signed-off-by: NBharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Acked-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> [AF: Keep calling cpu_exec_init() for CONFIG_USER_ONLY] Signed-off-by: NAndreas Färber <afaerber@suse.de>
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由 Bharata B Rao 提交于
Add an Error argument to cpu_exec_init() to let users collect the error. This is in preparation to change the CPU enumeration logic in cpu_exec_init(). With the new enumeration logic, cpu_exec_init() can fail if cpu_index values corresponding to max_cpus have already been handed out. Since all current callers of cpu_exec_init() are from instance_init, use error_abort Error argument to abort in case of an error. Signed-off-by: NBharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: NEduardo Habkost <ehabkost@redhat.com> Reviewed-by: NIgor Mammedov <imammedo@redhat.com> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Acked-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: NAndreas Färber <afaerber@suse.de>
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- 09 3月, 2015 1 次提交
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由 Cyril Bur 提交于
This patch adds basic support for the VTB. PowerISA: The Virtual Time Base (VTB) is a 64-bit incrementing counter. Virtual Time Base increments at the same rate as the Time Base until its value becomes 0xFFFF_FFFF_FFFF_FFFF (2 64 - 1); at the next increment its value becomes 0x0000_0000_0000_0000. There is no interrupt or other indication when this occurs. The operation of the Virtual Time Base has the following additional properties. 1. Loading a GPR from the Virtual Time Base has no effect on the accuracy of the Virtual Time Base. 2. Copying the contents of a GPR to the Virtual Time Base replaces the contents of the Virtual Time Base with the contents of the GPR. Signed-off-by: NCyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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- 07 1月, 2015 1 次提交
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由 Tom Musta 提交于
The Power8 processor implements the Transactional Memory Facility as defined in Power ISA 2.07. Update the initialization code to indicate this. Signed-off-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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- 03 1月, 2015 1 次提交
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NPavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 23 12月, 2014 1 次提交
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NPavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Reviewed-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 20 11月, 2014 1 次提交
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由 Fabien Chouteau 提交于
In the previous patch, the registers were added to init_proc_G2LE instead of init_proc_e300. Signed-off-by: NFabien Chouteau <chouteau@adacore.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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- 05 11月, 2014 1 次提交
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由 Bharata B Rao 提交于
Opcode table has direct, indirect and double indirect handlers, but ppc_cpu_unrealizefn() frees direct handlers which are never allocated and never frees double indirect handlers. Signed-off-by: NBharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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