1. 13 1月, 2011 7 次提交
  2. 12 1月, 2011 8 次提交
  3. 11 1月, 2011 4 次提交
  4. 10 1月, 2011 13 次提交
  5. 09 1月, 2011 3 次提交
  6. 08 1月, 2011 5 次提交
    • A
      tcg/mips: fix branch target change during code retranslation · d43ffce1
      Aurelien Jarno 提交于
      TCG on MIPS was trying to avoid changing the branch offset, but didn't
      due to a stupid typo. Fix it.
      Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      d43ffce1
    • A
      tcg/arm: fix qemu_st64 for big endian targets · 9a3abc21
      Aurelien Jarno 提交于
      Due to a typo, qemu_st64 doesn't properly byteswap the 32-bit low word of
      a 64 bit word before saving it. This patch fixes that.
      Acked-by: NAndrzej Zaborowski <balrogg@gmail.com>
      Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      9a3abc21
    • A
      tcg/arm: fix branch target change during code retranslation · c69806ab
      Aurelien Jarno 提交于
      QEMU uses code retranslation to restore the CPU state when an exception
      happens. For it to work the retranslation must not modify the generated
      code. This is what is currently implemented in ARM TCG.
      
      However on CPU that don't have icache/dcache/memory synchronised like
      ARM, this requirement is stronger and code retranslation must not modify
      the generated code "atomically", as the cache line might be flushed
      at any moment (interrupt, exception, task switching), even if not
      triggered by QEMU. The probability for this to happen is very low, and
      depends on cache size and associativiy, machine load, interrupts, so the
      symptoms are might happen randomly.
      
      This requirement is currently not followed in tcg/arm, for the
      load/store code, which basically has the following structure:
        1) tlb access code is written
        2) conditional fast path code is written
        3) branch is written with a temporary target
        4) slow path code is written
        5) branch target is updated
      The cache lines corresponding to the retranslated code is not flushed
      after code retranslation as the generated code is supposed to be the
      same. However if the cache line corresponding to the branch instruction
      is flushed between step 3 and 5, and is not flushed again before the
      code is executed again, the branch target is wrong. In the guest, the
      symptoms are MMU page fault at a random addresses, which leads to
      kernel page fault or segmentation faults.
      
      The patch fixes this issue by avoiding writing the branch target until
      it is known, that is by writing only the branch instruction first, and
      later only the offset.
      
      This fixes booting linux guests on ARM hosts (tested: arm, i386, mips,
      mipsel, sh4, sparc).
      Acked-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com>
      Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      c69806ab
    • A
      Merge branch 'linux-user-for-upstream' of git://gitorious.org/qemu-maemo/qemu · 497aebb9
      Aurelien Jarno 提交于
      * 'linux-user-for-upstream' of git://gitorious.org/qemu-maemo/qemu:
        Remove dead code for ARM semihosting commandline handling
        Fix commandline handling for ARM semihosted executables
        linux-user: Fix incorrect NaN detection in ARM nwfpe emulation
        softfloat: Implement floatx80_is_any_nan() and float128_is_any_nan()
        linux-user: Implement FS_IOC_FIEMAP ioctl
        linux-user: Support ioctls whose parameter size is not constant
        linux-user: Implement sync_file_range{,2} syscalls
      497aebb9
    • W
      Remove dead code for ARM semihosting commandline handling · 67af42ac
      Wolfgang Schildbach 提交于
      There are some bits in the code which were used to store the commandline for
      the semihosting call. These bits are now write-only and can be removed.
      Signed-off-by: NWolfgang Schildbach <wschi@dolby.com>
      Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
      Signed-off-by: NRiku Voipio <riku.voipio@iki.fi>
      67af42ac