- 11 6月, 2013 2 次提交
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由 Eduardo Habkost 提交于
Some CPU model fixes are going to be included and they will require compatibility properties in the pc-*-1.5 machine-types. Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Reviewed-by: NIgor Mammedov <imammedo@redhat.com> Signed-off-by: NAndreas Färber <afaerber@suse.de>
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由 Igor Mammedov 提交于
QMP command "{ 'execute': 'cpu-add', 'arguments': { 'id': -1 }}" may cause QEMU SIGSEGV at: piix4_cpu_hotplug_req () ... g->sts[cpu_id / 8] |= (1 << (cpu_id % 8)); ... Since for PC in current implementation id should be in range [0...maxcpus) and maxcpus is already checked, add check for lower bound and error out on incorrect value. Signed-off-by: NIgor Mammedov <imammedo@redhat.com> Signed-off-by: NAndreas Färber <afaerber@suse.de>
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- 10 6月, 2013 2 次提交
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由 Wendy Liang 提交于
If a stream notify function is not ready, it may re-populate the notify call- back to indicate it should be re-polled later. This break in this usage, as immediately following the notify() call, .notify is set to NULL. reverse the ordering of the notify call and NULL assignment accordingly. [PC: Reworked commit message] Signed-off-by: NWendy Liang <jliang@xilinx.com> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com>
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由 Stefan Weil 提交于
Obviously the code wanted to mask the lower bits but failed to do so because of a missing "<". cppcheck detected a conditional expression which was always true (1 < 7). Signed-off-by: NStefan Weil <sw@weilnetz.de> Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com>
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- 06 6月, 2013 3 次提交
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由 Andreas Färber 提交于
The implementation of the ATA FLUSH command invokes a flush at the block layer, which may on raw files on POSIX entail a synchronous fdatasync(). This may in some cases take so long that the SLES 11 SP1 guest driver reports I/O errors and filesystems get corrupted or remounted read-only. Avoid this by setting BUSY_STAT, so that the guest is made aware we are in the middle of an operation and no ATA commands are attempted to be processed concurrently. Addresses BNC#637297. Suggested-by: NGonglei (Arei) <arei.gonglei@huawei.com> Signed-off-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NKevin Wolf <kwolf@redhat.com> Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>
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由 Cornelia Huck 提交于
Interpretation of the ccws to register (configuration) indicators contained a thinko: We want to disallow reading from 0, but setting the indicator pointer to 0 is fine. Let's fix the handling for CCW_CMD_SET{,_CONF}_IND. Cc: qemu-stable@nongnu.org Signed-off-by: NCornelia Huck <cornelia.huck@de.ibm.com>
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由 Cornelia Huck 提交于
Fix an off-by-one error when indicating availablity of concurrent sense data. Cc: qemu-stable@nongnu.org Signed-off-by: NCornelia Huck <cornelia.huck@de.ibm.com>
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- 05 6月, 2013 1 次提交
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由 Stefan Hajnoczi 提交于
Use qemu_del_nic() instead of qemu_del_net_client() to correctly free the entire NICState. Cc: qemu-stable@nongnu.org Reported-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>
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- 04 6月, 2013 25 次提交
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由 Fam Zheng 提交于
We may want to include a driver in the whitelist for read only tasks such as diagnosing or exporting guest data (with libguestfs as a good example). This patch introduces a readonly whitelist option, and for backward compatibility, the old configure option --block-drv-whitelist is now an alias to rw whitelist. Drivers in readonly list is only permitted to open file readonly, and returns -ENOTSUP for RW opening. E.g. To include vmdk readonly, and others read+write: ./configure --target-list=x86_64-softmmu \ --block-drv-rw-whitelist=qcow2,raw,file,qed \ --block-drv-ro-whitelist=vmdk Signed-off-by: NFam Zheng <famz@redhat.com> Signed-off-by: NKevin Wolf <kwolf@redhat.com>
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由 Jean-Christophe DUBOIS 提交于
* Unify function and type naming * use dynamic cast whenever possible * simplify Debug printf. * use new style device intialization. Signed-off-by: NJean-Christophe DUBOIS <jcd@tribudubois.net> Reviewed-by: NPeter Chubb <peter.chubb@nicta.com.au> Message-id: 1369839656-24466-1-git-send-email-jcd@tribudubois.net Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Igor Mitsyanko 提交于
Even if we do not register newly created RAM MemoryRegion for migration with vmstate_register_ram_global() function, ram_save_setup() still saves this region to snapshot file with empty idstr=="". Consequently this results in error during VM loading in ram_load(). Register rom_mem for migration. Signed-off-by: NIgor Mitsyanko <i.mitsyanko@samsung.com> Message-id: 1368199981-45292-3-git-send-email-i.mitsyanko@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Igor Mitsyanko 提交于
Exynos SoC was misusing memory_region_init_ram_ptr(): this interface can safely be used only for memory regions which size is a multiple of target page size. Change chipid_and_omr memory to an mmio region to fix this. Signed-off-by: NIgor Mitsyanko <i.mitsyanko@samsung.com> Message-id: 1368199981-45292-2-git-send-email-i.mitsyanko@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Jean-Christophe DUBOIS 提交于
There is no common code between these 2 timer implementation. So it is better to split them. Signed-off-by: NJean-Christophe DUBOIS <jcd@tribudubois.net> Message-id: 1368990197-19694-1-git-send-email-jcd@tribudubois.net Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
QEMU models two (of the three) ACMD41 has two modes, "inquiry" and "first". The selection logic for which of the two is incorrect - it compares != 0 for the entire argument value rather than only bits 23:0 as per the spec. Fix. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 3ef0a7fd1b2f3ebb23b4fdeabcc14caf3fad6d71.1369622254.git.peter.crosthwaite@xilinx.com Reviewed-by: NIgor Mitsyanko <i.mitsyanko@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
The end of transfer check was occurring and potentially returning before the interrupt flag was checked. This means the interrupt will be missed if it occurs on the last packet. Fix by checking for the interrupt before checking for the end of transfer. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NIgor Mitsyanko <i.mitsyanko@gmail.com> Message-id: 9969ec154777957ec738fc4e539d68e7494d0081.1369370934.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
This message was printing out the data in decimal only, which is not very friendly to the debugging developer. Add hex variant in parenthesis to make it consistent with other similar messages in this module. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NIgor Mitsyanko <i.mitsyanko@gmail.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: d624179649137832eaa8caa263ef9589b4395d5e.1369370934.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
This interrupt is not risen after the last block is written to sd. It is mutually exclusive with the end of transfer conditions. Fix. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NIgor Mitsyanko <i.mitsyanko@gmail.com> Message-id: 7ca9fd3e03ce1bec94aff08f607c15a0ec3d3371.1369370934.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
The data_count variable was being reset on every transfer, including DMA transfer resumptions. This is incorrect, it should only be set on a new command. Manifests as a bug when using ADMA and there is a timer delay between ADMA frames where the fifo is left in a non empty state. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NIgor Mitsyanko <i.mitsyanko@gmail.com> Message-id: 15a98609cc32315211b0963091a8efd67522e160.1369370934.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
The LQSPI bus attachment supports byte/halfword and misaligned accesses. Fixed. Refactored the LQSPI cache to be byte-wise instead of word wise accordingly. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 5ec47b13563ad2d22105a1f26186d7756718394b.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Do 16 words per fifo flush. Increases performance and decreases debug verbosity. This data depth has no real hardware analogue, so just go with something that has reasonable performance. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 5621ee4621941d3639b5cacfdec26bd3148f31d5.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
The debug printfs on every SPI operation is extremely verbose. Add a second level of debug for this. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: f63478b8e5b29cc011cdc10e29f8537bb2fc2b5e.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
This is worth keeping track of when debugging the device model. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: d3b44ecf23d671798b062eee5dc362c716ea54cd.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
The QSPI controller was using byte-wide stripes when striping across the two flashes in dual parallel mode. The real hardware however uses individual bit striping. QEMU misbehaves in the (corner) case where data is written/read in dual-parallel mode and read/written back in single mode. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 718a61df1bf746ec06f6da44d12f8317af7b08ce.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
The CTRL register was RAZ/WI on some of the RW bits. Even though the function behind these bits is invalid in QEMU, they should still be guest accessible. Fix. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: b7aaad93163ce4af0c428635804ac7b77a567b25.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
The LQSPI mode is supposed to work via the automatic CS mode feature rather than manipulate CS lines itself. Now that auto CS is implemented remove LQSPIs CS mode override logic. There is still a need to manipulate the U_PAGE bit in LQSPI config register to implement dual-stack mode however. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 000c8dd54df09523f17052638100722ef0f5a3af.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Implement the automatic CS control feature. If the MANUAL_CS bit is cleared then the chip select stay de-asserted as long as the tx FIFO is empty. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 1d67383adc42761af715a93f161344b9284dfc9a.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
SPI has a mode where it automatically starts based on tx fifo occupancy. Implemented. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: f4e9accb5de87b526fff6ed937f63278db76533b.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Invalidate the LQSPI cached page when transitioning into LQSPI mode. Otherwise there is a possibility that the controller will return stale data to the guest when transitioning back to LQ_MODE after a page program. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 677490a6ee1953fe5d366e599d665de645ac84db.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
QSPI has a bigger FIFO than the regular SPI controller. Differentiate between the two with correct FIFO sizes for each. This is the first piece of class data for SPIPS, so this patch sees the creation of the XilinxSPIPSClass definition and assoicated QOM constructs. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: acee25dd5e203215cbc15ca5d3cb5d5b2efebe7b.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
You really need this is you want to track a guest banging on LQSPI. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 26e508da4af11058d37daa777064c9e5c2a69abb.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
The real hardware does not produce interrupts in LQSPI mode. Inhibit generation of interrupts when the LQ_MODE bit is set. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: dff794a06872009ea7e5733ce6adcff94d18bbd0.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
By default these interrupts are clear on read. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 999ff0091ed3cc3969a431bf55c00ef934cecc8e.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Make SPI and QSPI different classes. QSPIPS is setup as a child of SPIPS. Only QSPI has the LQSPI functionality, so move all that to the child class. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 2cdd0cadb5ba77ca02fde5cae627852dc9a64c71.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 03 6月, 2013 7 次提交
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由 Stefano Stabellini 提交于
Call kvmclock_create only if kvmclock_enabled. Use pc_init_pci on Xen rather than pc_init_pci_no_kvmclock. Signed-off-by: NStefano Stabellini <stefano.stabellini@eu.citrix.com>
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由 Stefano Stabellini 提交于
No need for xen_vcpu_init anymore: - the RTC emulator doesn't have any periodic timers continuously running even in absence of guest interactions anymore; - qemu_dummy_start_vcpu takes care of disabling TCG for us, so we don't need to do it manually here. Signed-off-by: NStefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: NAndreas Färber <afaerber@suse.de>
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由 Stefano Stabellini 提交于
We are currently setting the PCI hole to start at HVM_BELOW_4G_RAM_END, that is 0xf0000000. Start the PCI hole at 0xe0000000 instead, that is the same value used by pc_init1 and qemu-xen-traditional. Signed-off-by: NStefano Stabellini <stefano.stabellini@eu.citrix.com> CC: qemu-stable@nongnu.org
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由 Stefano Stabellini 提交于
This fixes a regression introduced by: commit 62fc403f Author: Igor Mammedov <imammedo@redhat.com> Date: Mon Apr 29 18:54:13 2013 +0200 target-i386: Attach ICC bus to CPU on its creation X86CPU should have parent bus so it could provide bus for child APIC. The commit makes it mandatory to pass a valid ICC bus to cpu_x86_create, but cpu_x86_init just passes NULL to it. xen_machine_pv uses cpu_x86_init, therefore it has been broken. This patch fixes the problem by removing the dummy CPU creation altogether from xen_init_pv, relying on the fact that QEMU can now cope with a machine without an emulated CPU. Signed-off-by: NStefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: NAndreas Färber <afaerber@suse.de> CC: imammedo@redhat.com CC: qemu-stable@nongnu.org
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由 Gerd Hoffmann 提交于
With all preparing pieces in place we can finally drop in the vmstate structs and the postload function. Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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由 Gerd Hoffmann 提交于
Factor out endpoint context initialization to a separate function. xhci live migration will need that too, in post_load. Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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由 Gerd Hoffmann 提交于
Factor out endpoint context allocation to a separate function. xhci live migration will need that too, in post_load. Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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