Removes a whole lot of unnecessary boilerplate code. Machines
don't need to be objects. The expansion of the SOC object model
for the RISC-V machines will happen in the future as SiFive
plans to add their FE310 and FU540 SOCs to QEMU. However, it
seems that this present boilerplate is complete unnecessary.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: NAlistair Francis <alistair.francis@wdc.com>

When load_elf is called with NULL as an argument to the
address translate callback, it does an identity translation.
This commit removes the redundant identity_translate callback.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: NAlistair Francis <alistair.francis@wdc.com>

Another case of replacing hard coded constants, this time
referring to the definition in the virt machine's memmap.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: NAlistair Francis <alistair.francis@wdc.com>

This makes 'qemu-system-riscv64 -machine help' output more tidy
and consistent.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: NAlistair Francis <alistair.francis@wdc.com>

The RISC-V device-tree code has a number of hard-coded
constants and this change moves them into header enums.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: NAlistair Francis <alistair.francis@wdc.com>

Change all the uses of serial_hds[] to go via the new
serial_hd() function. Code change produced with:
 find hw -name '*.[ch]' | xargs sed -i -e 's/serial_hds\[\([^]]*\)\]/serial_hd(\1)/g'
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NThomas Huth <thuth@redhat.com>
Message-id: 20180420145249.32435-8-peter.maydell@linaro.org

This adds RISC-V into the build system enabling the following targets:

- riscv32-softmmu
- riscv64-softmmu
- riscv32-linux-user
- riscv64-linux-user

This adds defaults configs for RISC-V, enables the build for the RISC-V
CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh'
script is updated to add the RISC-V ELF magic.

Expected checkpatch errors for consistency reasons:

ERROR: line over 90 characters
FILE: scripts/qemu-binfmt-conf.sh
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: NSagar Karandikar <sagark@eecs.berkeley.edu>
Signed-off-by: NMichael Clark <mjc@sifive.com>

This provides a RISC-V Board compatible with the the SiFive Freedom U SDK.
The following machine is implemented:

- 'sifive_u'; CLINT, PLIC, UART, device-tree
Acked-by: NRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: NSagar Karandikar <sagark@eecs.berkeley.edu>
Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>

This provides a RISC-V Board compatible with the the SiFive Freedom E SDK.
The following machine is implemented:

- 'sifive_e'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM
Acked-by: NRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: NSagar Karandikar <sagark@eecs.berkeley.edu>
Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>

Simple model of the PRCI  (Power, Reset, Clock, Interrupt) to emulate
register reads made by the SDK BSP.
Acked-by: NRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>

QEMU model of the UART on the SiFive E300 and U500 series SOCs.
BBL supports the SiFive UART for early console access via the SBI
(Supervisor Binary Interface) and the linux kernel SBI console.

The SiFive UART implements the pre qom legacy interface consistent
with the 16550a UART in 'hw/char/serial.c'.
Acked-by: NRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: NStefan O'Rear <sorear2@gmail.com>
Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>

RISC-V machine with device-tree, 16550a UART and VirtIO MMIO.
The following machine is implemented:

- 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree
Acked-by: NRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>

Test finisher memory mapped device used to exit simulation.
Acked-by: NRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>

RISC-V machines compatble with Spike aka riscv-isa-sim, the RISC-V
Instruction Set Simulator. The following machines are implemented:

- 'spike_v1.9.1'; HTIF console, config-string, Privileged ISA Version 1.9.1
- 'spike_v1.10'; HTIF console, device-tree, Privileged ISA Version 1.10
Acked-by: NRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: NSagar Karandikar <sagark@eecs.berkeley.edu>
Signed-off-by: NMichael Clark <mjc@sifive.com>

The PLIC (Platform Level Interrupt Controller) device provides a
parameterizable interrupt controller based on SiFive's PLIC specification.
Acked-by: NRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: NStefan O'Rear <sorear2@gmail.com>
Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>

The CLINT (Core Local Interruptor) device provides real-time clock, timer
and interprocessor interrupts based on SiFive's CLINT specification.
Acked-by: NRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: NSagar Karandikar <sagark@eecs.berkeley.edu>
Signed-off-by: NStefan O'Rear <sorear2@gmail.com>
Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>

Holds the state of a heterogenous array of RISC-V hardware threads.
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: NSagar Karandikar <sagark@eecs.berkeley.edu>
Signed-off-by: NMichael Clark <mjc@sifive.com>

HTIF (Host Target Interface) provides console emulation for QEMU. HTIF
allows identical copies of BBL (Berkeley Boot Loader) and linux to run
on both Spike and QEMU. BBL provides HTIF console access via the
SBI (Supervisor Binary Interface) and the linux kernel SBI console.

The HTIT chardev implements the pre qom legacy interface consistent
with the 16550a UART in 'hw/char/serial.c'.
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: NSagar Karandikar <sagark@eecs.berkeley.edu>
Signed-off-by: NStefan O'Rear <sorear2@gmail.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>