- 20 1月, 2017 35 次提交
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由 Peter Maydell 提交于
The PSCI spec states that a CPU_ON call should cause the new CPU to be started in the highest implemented Non-secure exception level. We were incorrectly starting it at the exception level of the caller, which happens to be correct if EL2 is not implemented. Implement the correct logic as described in the PSCI 1.0 spec section 6.4: * if EL2 exists and SCR_EL3.HCE is set: start in EL2 * otherwise start in EL1 Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: NAndrew Jones <drjones@redhat.com> Tested-by: NAndrew Jones <drjones@redhat.com> Message-id: 1483977924-14522-17-git-send-email-peter.maydell@linaro.org
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由 Andrew Jones 提交于
Signed-off-by: NAndrew Jones <drjones@redhat.com> Acked-by: NAlistair Francis <alistair.francis@xilinx.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1483977924-14522-16-git-send-email-peter.maydell@linaro.org [PMM: look at vms->psci_conduit rather than vms->virt to decide whether to use HVC or SMC, and report no PSCI support at all for the 'PSCI disabled' case] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
If we are giving the guest a CPU with EL2, it is likely to want to use the HVC instruction itself, for instance for providing PSCI to inner guest VMs. This makes using HVC as the PSCI conduit for the outer QEMU a bad idea. We will want to use SMC instead is this case: this makes sense because QEMU's PSCI implementation is effectively an emulation of functionality provided by EL3 firmware. Add code to support selecting the PSCI conduit to use, rather than hardcoding use of HVC. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: NAndrew Jones <drjones@redhat.com> Message-id: 1483977924-14522-15-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Implement the architecturally required traps from NS EL1 to EL2 for the CPU interface registers. These fall into several different groups: * group-0-only registers all trap if ICH_HRC_EL2.TALL0 is set (exactly the registers covered by gicv3_fiq_access()) * group-1-only registers all trap if ICH_HRC_EL2.TALL1 is set (exactly the registers covered by gicv3_irq_access()) * DIR traps if ICH_HCR_EL2.TC or ICH_HCR_EL2.TDIR are set * PMR, RPR, CTLR trap if ICH_HCR_EL2.TC is set * SGI0R, SGI1R, ASGI1R trap if ICH_HCR_EL2.TC is set or if HCR_EL2.IMO or HCR_EL2.FMO are set We split DIR and the SGI registers out into their own access functions, leaving the existing gicv3_irqfiq_access() just handling PMR, RPR and CTLR. This commit doesn't implement support for trapping on HSTR_EL2.T12 for the 32-bit registers, as we don't implement any of those per-coprocessor trap bits currently and probably will want to do those in some more centralized way. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1483977924-14522-14-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Implement the function which signals virtual interrupts to the CPU as appropriate following CPU interface state changes. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1483977924-14522-13-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Implement the two remaining ICV_ registers: EOIR and IAR. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1483977924-14522-12-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Implement the the ICV_ registers HPPIR, DIR and RPR. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1483977924-14522-11-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
If the HCR_EL2.IMO or FMO bits are set, accesses to ICC_ system registers are redirected to be accesses to ICV_ registers (the guest-visible interface to the virtual interrupt controller). Implement this behaviour for the ICV_ registers which are simple accessors to the underlying register state. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1483977924-14522-10-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The GICv3 virtualization interface includes system registers accessible only to the hypervisor which form the control interface for interrupt virtualization. Implement these registers. The function gicv3_cpuif_virt_update() which determines whether it needs to signal vIRQ, vFIQ or a maintenance interrupt is introduced here as a stub function -- its implementation will be added in a subsequent commit. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1483977924-14522-9-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
As the first step in adding support for the virtualization extensions to the GICv3 emulation: * add the necessary data fields to the state structures * add the fields to the migration state, as a subsection which is only present if virtualization is enabled The use of a subsection means we retain migration compatibility as EL2 is not enabled on any CPUs currently. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NAlistair Francis <alistair.francis@xilinx.com> Message-id: 1483977924-14522-8-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Add defines to gicv3_internal.h for fields in the ICH_* system registers which form the GIC virtualization control interface. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1483977924-14522-7-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Add fields to the ARMCPU structure to allow CPU classes to specify the configurable aspects of their GIC CPU interface. In particular, the virtualization support allows different values for number of list registers, priority bits and preemption bits. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NAlistair Francis <alistair.francis@xilinx.com> Message-id: 1483977924-14522-6-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Wire the new VIRQ, VFIQ and maintenance interrupt lines from the GIC to each CPU. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1483977924-14522-5-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The GICv3 support for virtualization includes an outbound maintenance interrupt signal which is asserted when the CPU interface wants to signal to the hypervisor that it needs attention. Expose this as an outbound GPIO line from the CPU object which can be wired up as a physical interrupt line by the board code (as we do already for the CPU timers). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Message-id: 1483977924-14522-4-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Augment the GIC's QOM device interface by adding two new sets of sysbus IRQ lines, to signal VIRQ and VFIQ to each CPU. We never use these, but it's helpful to keep the v2-and-earlier GIC's external interface in line with that of the GICv3 to avoid board code having to add extra code conditional on which version of the GIC is in use. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1483977924-14522-3-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Augment the GICv3's QOM device interface by adding two new sets of sysbus IRQ lines, to signal VIRQ and VFIQ to each CPU. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Message-id: 1483977924-14522-2-git-send-email-peter.maydell@linaro.org
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由 Ard Biesheuvel 提交于
Linux for arm64 v4.10 and later will complain if the ECAM config space is not reserved in the ACPI namespace: acpi PNP0A08:00: [Firmware Bug]: ECAM area [mem 0x3f000000-0x3fffffff] not reserved in ACPI namespace The rationale is that OSes that don't consume the MCFG table should still be able to infer that the PCI config space MMIO region is occupied. So update the ACPI table generation routine to add this reservation. Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org> Message-id: 1484328738-21149-1-git-send-email-ard.biesheuvel@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Shannon Zhao 提交于
Using -cpu cortex-a9 (or any other unsupported CPU) with the virt board will cause QEMU to segmentation fault. This bug was introduced in commit 9ac4ef77, which incorrectly added a NULL terminator when converting the VirtBoardInfo array into a simple array of strings defining the valid CPUs. The cpuname_valid() loop already has a termination condition based on ARRAY_SIZE, so the NULL is spurious and causes the strcmp() to segfault if we reach it. Delete the NULL. Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Message-id: 1484619334-10488-1-git-send-email-zhaoshenglong@huawei.com [PMM: expanded commit message] Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
Create a ROM region, using the default size of the mapping window for the CE0 FMC flash module, and fill it with the flash content. This is a little hacky but until we can boot from a MMIO region, it seems difficult to do anything else. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NJoel Stanley <joel@jms.id.au> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1483979087-32663-11-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
The Aspeed SMC controllers have a mode (Command mode) in which accesses to the flash content are no different than doing MMIOs. The controller generates all the necessary commands to load (or store) data in memory. So add a couple of tests doing direct reads and writes on the AHB bus. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1483979087-32663-10-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
Let's make sure when each test is run that the flash object is in an initial state and did not keep configuration from the previous tests. Signed-off-by: NCédric Le Goater <clg@kaod.org> Message-id: 1483979087-32663-9-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
The Aspeed SMC controllers have a mode (Command mode) in which accesses to the flash content are no different than doing MMIOs. The controller generates all the necessary commands to load (or store) data in memory. However, accesses are restricted to the segment window assigned the the flash module by the controller. This window is defined by the Segment Address Register. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1483979087-32663-8-git-send-email-clg@kaod.org [PMM: Deleted now-unused aspeed_smc_is_usermode() function] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
The SPI controller of the AST2400 SoC has less registers. So we can adjust the size of the memory region holding the registers depending on the controller type. We can also remove the guest_error logging which is useless as the range of the region is strict enough. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NJoel Stanley <joel@jms.id.au> Message-id: 1483979087-32663-7-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
This is getting difficult to read. Also add a 'has_dma' field for each controller type. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NJoel Stanley <joel@jms.id.au> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1483979087-32663-6-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
On the AST2500 SoC, the FMC controller flash type is fixed to SPI for CE0 and CE1 and 4BYTE mode is autodetected for CE0. On the AST2400 SoC, the FMC controller flash type and 4BYTE mode are strapped with register SCU70. We use the default settings from the palmetto-bmc machine for now. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NJoel Stanley <joel@jms.id.au> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1483979087-32663-5-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
Change the routines prototype to use a 'AspeedSMCFlash *' instead of 'AspeedSMCState *'. The result will help in making future changes clearer. Also change aspeed_smc_update_cs() which uselessly loops on all slave devices to update their status. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NJoel Stanley <joel@jms.id.au> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1483979087-32663-4-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
Instead, we can simply set the irq level when unselecting the slave devices. This change prepares ground for a subsequent cleanup of the aspeed_smc_update_cs() routine which uselessly loops on all slaves to update their status. Signed-off-by: NCédric Le Goater <clg@kaod.org> Message-id: 1483979087-32663-3-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
This is useless as reset will be called later on. Signed-off-by: NCédric Le Goater <clg@kaod.org> Acked-by: NMarcin Krzemiński <mar.krzeminski@gmail.com> Message-id: 1483979087-32663-2-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
The DBGVCR_EL2 system register is needed to run a 32-bit EL1 guest under a Linux EL2 64-bit hypervisor. Its only purpose is to provide AArch64 with access to the state of the DBGVCR AArch32 register. Since we only have a dummy DBGVCR, implement a corresponding dummy DBGVCR32_EL2. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com>
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由 Peter Maydell 提交于
To run a VM in 32-bit EL1 our AArch32 interrupt handling code needs to be able to cope with VIRQ and VFIQ exceptions. These behave like IRQ and FIQ except that we don't need to try to route them to Monitor mode. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com>
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由 Marcin Krzeminski 提交于
n25q00 and mt25q01 devices share the same JEDEC ID. The difference between those two devices is number of dies and one bit in extended JEDEC bytes. This commit adds proper entry for both devices by introduction the number of dies and and new 25q00 entries. Signed-off-by: NMarcin Krzeminski <mar.krzeminski@gmail.com> Reviewed-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20170108083854.5006-4-mar.krzeminski@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Marcin Krzeminski 提交于
Modern big flash NOR devices consist of more than one die. Some of them do not support chip erase and instead have a die erase command that can erase one die only. This commit adds support for defining the number of dies in the chip, and adds support for die erase command. The NOR flash model is not strict, so no option to disable chip erase has been added. Signed-off-by: NMarcin Krzeminski <mar.krzeminski@gmail.com> Reviewed-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20170108083854.5006-3-mar.krzeminski@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Marcin Krzeminski 提交于
Some flash chips have additional page program opcode that takes only 4 byte address. This commit adds support for such command in Qemu. Signed-off-by: NMarcin Krzeminski <mar.krzeminski@gmail.com> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20170108083854.5006-2-mar.krzeminski@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alastair D'Silva 提交于
The imx25 chip provides 3 i2c buses, but they have all been named "i2c", which makes it difficult to predict which bus a device will be connected to when specified on the command line. This patch addresses the issue by naming the buses uniquely: i2c-bus.0 i2c-bus.1 i2c-bus.2 Signed-off-by: NAlastair D'Silva <alastair@d-silva.org> Message-id: 20170105043430.3176-2-alastair@au1.ibm.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
add OpenSPARC T1 emulation # gpg: Signature made Wed 18 Jan 2017 22:25:47 GMT # gpg: using RSA key 0x3360C3F7411A125F # gpg: Good signature from "Artyom Tarasenko <atar4qemu@gmail.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 2AD8 6149 17F4 B2D7 05C0 BB12 3360 C3F7 411A 125F * remotes/artyom/tags/pull-sun4v-20170118: (30 commits) target-sparc: fix up niagara machine target-sparc: move common cpu initialisation routines to sparc64.c target-sparc: implement sun4v RTC target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs target-sparc: store the UA2005 entries in sun4u format target-sparc: implement UA2005 ASI_MMU (0x21) target-sparc: add more registers to dump_mmu target-sparc: implement auto-demapping for UA2005 CPUs target-sparc: allow 256M sized pages target-sparc: simplify ultrasparc_tsb_pointer target-sparc: implement UA2005 TSB Pointers target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs target-sparc: replace the last tlb entry when no free entries left target-sparc: ignore writes to UA2005 CPU mondo queue register target-sparc: allow priveleged ASIs in hyperprivileged mode target-sparc: use direct address translation in hyperprivileged mode target-sparc: fix immediate UA2005 traps target-sparc: implement UA2005 rdhpstate and wrhpstate instructions target-sparc: implement UA2005 GL register target-sparc: implement UA2005 hypervisor traps ... Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 19 1月, 2017 5 次提交
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由 Peter Maydell 提交于
tcg/i386 fixes # gpg: Signature made Tue 17 Jan 2017 22:58:04 GMT # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B * remotes/rth/tags/pull-tcg-20170117: tcg/i386: Always use TZCNT when available Revert "tcg/i386: Rely on undefined/undocumented behaviour of BSF/BSR" Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Artyom Tarasenko 提交于
Remove the Niagara stub implementation from sun4u.c and add a machine, compatible with Legion simulator from the OpenSPARC T1 project. The machine uses the firmware supplied with the OpenSPARC T1 project, http://download.oracle.com/technetwork/systems/opensparc/OpenSPARCT1_Arch.1.5.tar.bz2 in the directory S10image/, and is able to boot the supplied Solaris 10 image. Note that for compatibility with the naming conventions for SPARC machines the new machine name is lowercase niagara. Signed-off-by: NArtyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Artyom Tarasenko 提交于
Signed-off-by: NArtyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Artyom Tarasenko 提交于
Signed-off-by: NArtyom Tarasenko <atar4qemu@gmail.com>
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由 Artyom Tarasenko 提交于
In OpenSPARC T1+ TWINX ASIs in store instructions are aliased with Block Initializing Store ASIs. "UltraSPARC T1 Supplement Draft D2.1, 14 May 2007" describes them in the chapter "5.9 Block Initializing Store ASIs" Integer stores of all sizes are allowed with these ASIs. Signed-off-by: NArtyom Tarasenko <atar4qemu@gmail.com>
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