Only allocate t1 when needed.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Load/store operations use macros for historical reasons. Now that there
is no point in keeping them, replace them by direct calls to qemu_ld/st.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Rework *raise_exception*() functions so that they can be called from
other helpers, passing the return address as an argument.

Use do_raise_exception() function in update_fcr31() to correctly restore
the CPU state after an FPU exception.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

softfloat already has a few constants defined, use them instead of
redefining them in target-mips.

Rename FLOAT_SNAN32 and FLOAT_SNAN64 to FP_TO_INT32_OVERFLOW and
FP_TO_INT64_OVERFLOW as even if they have the same value, they are
technically different (and defined differently in the MIPS ISA).

Remove the unused constants.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Instead of accessing the flags from the floating point control
register after updating it, read the softfloat flags.

This is just code cleanup and should not change the behaviour.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

For each FPU instruction that can trigger an FPU exception, to call
call update_fcr31() after.

Remove the manual NaN assignment in case of float to float operation, as
softfloat is already taking care of that. However for float to int
operation, the value has to be changed to the MIPS one. In the cvtpw_ps
case, the two registers have to be handled separately to guarantee
a correct final value in both registers.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Instead of clearing the softfloat exception flags before each floating
point instruction, reset them to 0 in update_fcr31() when an exception
is detected.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Use the new softfloat floatXX_muladd() functions to implement the madd,
msub, nmadd and nmsub instructions. At the same time replace the name of
the helpers by the name of the instruction, as the only reason for the
previous names was to keep the macros simple.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add a pickNaNMulAdd function for MIPS, implementing NaN propagation
rules for MIPS fused multiply-add instructions.

Cc: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

When the CPU state after a possible retranslation is going to be handled
through code retranslation, we don't need to save the CPU state before.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

When the CPU state is restored through retranslation after an exception,
btarget should also be restored.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Commit 9c43b68d do not correctly check
for dead outputs when they need to be synced to memory in case of
half-dead operations.

Fix that by applying the same pattern than for the default case.
Tested-by: NStefan Weil <sw@weilnetz.de>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Mark helper functions that raise exceptions, but otherwise do not
change TCG register state, with TCG_CALL_NO_WG.
Signed-off-by: NRichard Henderson <rth@twiddle.net>

As the block layer may decide to flush bottom-halfs while the machine is
still initializing (e.g. to read geometry data from the disk), our
postponed open event may be processed before the last frontend
registered with a muxed chardev.

Until the semantics of BHs have been clarified, use an expired timer to
achieve the same effect (suggested by Paolo Bonzini). This requires to
perform the alarm timer initialization earlier as otherwise timer
subsystem can be used before being ready.
Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com>

All switch() decoding instruction have a default entry, so it is possible
to have unused enum entries. Remove conditional definitions of MIPS64
opcode enums, as it only makes the code less readable.
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Change DSP r1 & DSP r2 into microMIPS DSP encodings in TODO file.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP testcases.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add 74kf and mips64dspr2-generic-cpu model for test.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP Accumulator and DSPControl Access instructions.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP Compare-Pick instructions.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP Bit/Manipulation instructions.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP Multiply instructions.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP GPR-Based Shift instructions.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP Arithmetic instructions.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP Load instructions.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP Branch instructions.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP resources access check.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add internal functions using by MIPS ASE DSP instructions.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add missing stubs to win32 to fix link failure.
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
Reported-by: NPaolo Bonzini <pbonzini@redhat.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

With i386-linux-user target on x86_64 host, this does not introduce any new test
failures.
Signed-off-by: NCatalin Patulea <catalinp@google.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

gcc will silently accept unrecognized -Wno-wombat warning suppression
options (it only mentions them if it has to print a compiler warning
for some other reason). Since we already run a check for whether gcc
recognizes the warning options we use, we can easily make this use
the positive sense of the option when checking for support for the
suppression option. This doesn't have any effect except that it avoids
gcc emitting extra messages about unrecognized command line options
when it is printing other warning messages.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NStefan Weil <sw@weilnetz.de>
Reviewed-by: NIgor Mitsyanko <i.mitsyanko@samsung.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

There is some read-after-write error within the OP=2 insns which
prevents setting cpu_dst to the real output register.  Until this
is found and fixed, always write to a temporary first.

Cc: Blue Swirl <blauwirbel@gmail.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Tested-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

* 'qspi.2' of git://developer.petalogix.com/public/qemu:
  xilinx_zynq: added QSPI controller
  xilinx_spips: Generalised to model QSPI
  m25p80: Support for Quad SPI

* 's390-for-upstream' of git://repo.or.cz/qemu/agraf:
  s390: sclp ascii console support
  s390: sclp signal quiesce support
  s390: sclp event support
  s390: sclp base support
  s390: use sync regs for register transfer
  s390/kvm_stat: correct sys_perf_event_open syscall number
  s390x: fix -initrd in virtio machine

MIPS32 and later instruction sets have a multiplication instruction
directly operating on GPRs. It only produces a 32-bit result but
it is exactly what is needed by QEMU.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

The memory core drops regions that are hidden by another region (for example,
during BAR sizing), but it doesn't do so correctly if the lower address of the
existing range is below the lower address of the new range.

Example (qemu-system-mips -M malta -kernel vmlinux-2.6.32-5-4kc-malta
         -append "console=ttyS0"  -nographic -vga cirrus):

Existing range: 10000000-107fffff
New range:      100a0000-100bffff

Correct behaviour: drop new range
Incorrect behaviour: add new range

Fix by taking this case into account (previously we only considered
equal lower boundaries).
Tested-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NAvi Kivity <avi@redhat.com>
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>

virtio,pci infrastructure

This includes infrastructure patches that don't do much by themselves
but should help vfio and q35 make progress.
Also included is rework of virtio-net to use iovec APIs
for vector access - helpful to make it more secure
and in preparation for a new feature that will allow
arbitrary s/g layout for guests.
Also included is a pci bridge bugfix by Avi.
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>

* mst/tags/for_anthony: (25 commits)
  pci: avoid destroying bridge address space windows in a transaction
  virtio-net: enable mrg buf header in tap on linux
  virtio-net: test peer header support at init time
  virtio-net: minor code simplification
  virtio-net: simplify rx code
  virtio-net: switch tx to safe iov functions
  virtio-net: first s/g is always at start of buf
  virtio-net: refactor receive_hdr
  virtio-net: use safe iov operations for rx
  virtio-net: avoid sg copy
  iov: add iov_cpy
  virtio-net: track host/guest header length
  pcie: Convert PCIExpressHost to use the QOM.
  pcie: pass pcie window size to pcie_host_mmcfg_update()
  pci: Add class 0xc05 as 'SMBus'
  pci: introduce pci_swizzle_map_irq_fn() for standardized interrupt pin swizzle
  pci_ids: add intel 82801BA pci-to-pci bridge id
  pci: pci capability must be in PCI space
  pci: make each capability DWORD aligned
  qemu: enable PV EOI for qemu 1.3
  ...
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>

This code adds console support  by implementing SCLP's ASCII Console
Data event. This is the same console as LPARs ASCII console or z/VMs
sysascii.

The console can be specified manually with something like
-chardev stdio,id=charconsole0 -device sclpconsole,chardev=charconsole0,id=console0

Newer kernels will autodetect that console and prefer that over virtio
console.

When data is received from the character layer it creates a service
interrupt to trigger a Read Event Data command from the guest that will
pick up the received character byte-stream.
When characters are echo'ed by the linux guest a Write Event Data occurs
which is forwarded by the Event Facility to the console that supports
a corresponding mask value.
Console resizing is not supported.
The character layer byte-stream is buffered using a fixed size iov
buffer.
Signed-off-by: NHeinz Graalfs <graalfs@linux.vnet.ibm.com>
Signed-off-by: NChristian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: NJens Freimann <jfrei@linux.vnet.ibm.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

This implements the sclp signal quiesce event via the SCLP Event
Facility.
This allows to gracefully shutdown a guest by using system_powerdown
notifiers. It creates a service interrupt that will trigger a
Read Event Data command from the guest. This code will then add an
event that is interpreted by linux guests as ctrl-alt-del.
Signed-off-by: NHeinz Graalfs <graalfs@linux.vnet.ibm.com>
Signed-off-by: NChristian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: NJens Freimann <jfrei@linux.vnet.ibm.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>