- 22 12月, 2012 1 次提交
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由 Max Filippov 提交于
Zero out tcg_ctx.gen_opc_instr_start for instructions representing the last guest opcode in the TB. Cc: qemu-stable@nongnu.org Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 19 12月, 2012 5 次提交
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 16 12月, 2012 1 次提交
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由 Blue Swirl 提交于
Refactor common code around calls to cpu_restore_state(). tb_find_pc() has now no external users, make it static. Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 15 12月, 2012 1 次提交
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由 Max Filippov 提交于
With MMU option xtensa architecture has two TLBs: ITLB and DTLB. ITLB is only used for code access, DTLB is only for data. However TLB entries in both TLBs have attribute field controlling write and exec access. These bits need to be properly masked off depending on TLB type before being used as tlb_set_page prot argument. Otherwise the following happens: (1) ITLB entry for some PFN gets invalidated (2) DTLB entry for the same PFN gets updated, attributes allow code execution (3) code at the page with that PFN is executed (possible due to step 2), entry for the TB is written into the jump cache (4) QEMU TLB entry for the PFN gets replaced with an entry for some other PFN (5) code in the TB from step 3 is executed (possible due to jump cache) and it accesses data, for which there's no DTLB entry, causing DTLB miss exception (6) re-translation of the TB from step 5 is attempted, but there's no QEMU TLB entry nor xtensa ITLB entry for that PFN, which causes ITLB miss exception at the TB start address (7) ITLB miss exception is handled by the guest, but execution is resumed from the beginning of the faulting TB (the point where ITLB miss occured), not from the point where DTLB miss occured, which is wrong. With that fix the above scenario causes ITLB miss exception (that used to be step 7) at step 3, right at the beginning of the TB. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Cc: qemu-stable@nongnu.org Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 09 12月, 2012 6 次提交
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由 Max Filippov 提交于
Use movcond for all sorts of conditional moves, ABS, CLAMPS, MIN/MAX opcodes. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
The Miscellaneous Special Registers Option provides zero to four scratch registers within the processor readable and writable by RSR, WSR, and XSR. These registers are privileged. They may be useful for some application-specific exception and interrupt processing tasks in the kernel. The MISC registers are undefined after reset. See ISA, 4.7.3 for details. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
There are read-only (DEBUGCAUSE, PRID) and write-only (INTCLEAR) SRs, and INTERRUPT/INTSET SR allows rsr/wsr, but not xsr. Raise illeagal opcode exception on illegal access to these SRs. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
Beginning with the RA-2004.1 release, SR access instructions (rsr, wsr, xsr) are associated with their corresponding SR and raise illegal opcode exception in case the register is not configured for the core. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
In XEA1, the Options for Memory Protection and Translation and the corresponding TLB management instructions are not available. Instead, functionality similar to the Region Protection Option is available through the cache attribute register. See ISA, A.2.14 for details. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
ATOMCTL SR controls s32c1i opcode behavior depending on targeted memory type. See ISA, 4.3.12.4 for details. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 08 12月, 2012 3 次提交
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由 Evgeny Voevodin 提交于
Signed-off-by: NEvgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Evgeny Voevodin 提交于
Signed-off-by: NEvgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Evgeny Voevodin 提交于
Signed-off-by: NEvgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 17 11月, 2012 2 次提交
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由 Evgeny Voevodin 提交于
Signed-off-by: NEvgeny Voevodin <e.voevodin@samsung.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Evgeny Voevodin 提交于
Signed-off-by: NEvgeny Voevodin <e.voevodin@samsung.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 10 11月, 2012 1 次提交
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由 Blue Swirl 提交于
Pass around CPUArchState instead of using global cpu_single_env. Signed-off-by: NBlue Swirl <blauwirbel@gmail.com> Acked-by: NMax Filippov <jcmvbkbc@gmail.com> Reviewed-by: NAndreas Färber <afaerber@suse.de>
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- 31 10月, 2012 1 次提交
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由 Andreas Färber 提交于
For target-mips also change the return type to bool. Make include paths for cpu-qom.h consistent for alpha and unicore32. Signed-off-by: NAndreas Färber <afaerber@suse.de> [AF: Updated new target-openrisc function accordingly] Acked-by: Richard Henderson <rth@twiddle.net> (for alpha)
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- 28 10月, 2012 1 次提交
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由 Aurelien Jarno 提交于
Rename helper flags to the new ones. This is purely a mechanical change, it's possible to use better flags by looking at the helpers. Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 23 10月, 2012 1 次提交
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由 Avi Kivity 提交于
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are reserved) and its purpose doesn't match the name (most target_phys_addr_t addresses are not target specific). Replace it with a finger-friendly, standards conformant hwaddr. Outstanding patchsets can be fixed up with the command git rebase -i --exec 'find -name "*.[ch]" | xargs s/target_phys_addr_t/hwaddr/g' origin Signed-off-by: NAvi Kivity <avi@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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- 06 10月, 2012 1 次提交
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由 Aurelien Jarno 提交于
Now that "and" with 0xff, 0xffff and 0xffffffff and "shr" with 0 shift are optimized in tcg/tcg-op.h there is no need to do it in target-xtensa/translate.c. Acked-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 28 9月, 2012 1 次提交
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由 Richard Henderson 提交于
For all targets that currently call tcg_gen_debug_insn_start, add CPU_LOG_TB_OP_OPT to the condition that gates it. This is useful for comparing optimization dumps, when the pre-optimization dump is merely noise. Signed-off-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 23 9月, 2012 7 次提交
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由 Max Filippov 提交于
In case Coprocessor Context option is enabled CPENABLE SR bits control whether access to coprocessors is allowed or would rise one of CoprocessorXDisabled exceptions. See ISA, 4.4.5 for more details. FP is coprocessor 0. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
These are comparison and conditional move opcodes. See ISA, 4.3.10 for more details. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
These are FP to integer and integer to FP conversion opcodes. See ISA, 4.3.10 for more details. Note that ISA description for utrunc.s is currently incorrect and will be fixed in future revisions. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
These are FP arithmetic opcodes. See ISA, 4.3.10 for more details. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
These are load/store instructions for FP registers with immediate or register index and optional base post-update. See ISA, 4.3.10 for more details. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
There are 16 32-bit FP registers (f0 - f15), control and status user registers (fcr, fsr). See ISA, 4.3.10 for more details. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 21 9月, 2012 2 次提交
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由 Max Filippov 提交于
Unconditional gen_check_loop_end at the end of disas_xtensa_insn can emit tcg_gen_goto_tb with slot id already used in the TB (e.g. when TB ends at LEND with a branch). Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Cc: qemu-stable <qemu-stable@nongnu.org> Signed-off-by: Nmalc <av1474@comtv.ru>
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由 Max Filippov 提交于
extui opcode only uses lowermost op1 bit for sa4. Reported-by: Nmalc <av1474@comtv.ru> Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Cc: qemu-stable <qemu-stable@nongnu.org> Signed-off-by: Nmalc <av1474@comtv.ru>
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- 08 9月, 2012 1 次提交
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由 Max Filippov 提交于
Put the following errno value mappings under #ifdef: xtensa-semi.c: In function 'errno_h2g': xtensa-semi.c:113: error: 'ENOTBLK' undeclared (first use in this function) xtensa-semi.c:113: error: (Each undeclared identifier is reported only once xtensa-semi.c:113: error: for each function it appears in.) xtensa-semi.c:113: error: array index in initializer not of integer type xtensa-semi.c:113: error: (near initialization for 'guest_errno') xtensa-semi.c:124: error: 'ETXTBSY' undeclared (first use in this function) xtensa-semi.c:124: error: array index in initializer not of integer type xtensa-semi.c:124: error: (near initialization for 'guest_errno') xtensa-semi.c:134: error: 'ELOOP' undeclared (first use in this function) xtensa-semi.c:134: error: array index in initializer not of integer type xtensa-semi.c:134: error: (near initialization for 'guest_errno') Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 06 9月, 2012 1 次提交
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由 Max Filippov 提交于
Guest errno values are taken from the newlib. Convert only those errno values that can be returned from used system calls. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 01 9月, 2012 1 次提交
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由 Max Filippov 提交于
This prevents guest from proceeding with uninitialised garbage returned from unimplemented simcalls. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 10 8月, 2012 1 次提交
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由 Max Filippov 提交于
This makes usable default for -cpu option both for qemu-system-xtensa and qemu-system-xtensaeb fixing the following error: $ qemu-system-xtensaeb -M sim Unable to find CPU definition Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Tested-by: NMarkus Armbruster <armbru@redhat.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 28 7月, 2012 1 次提交
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由 Max Filippov 提交于
Quote from ISA, 2.1: For most Xtensa instructions, bit numbering is irrelevant; only the BBC and BBS instructions assign bit numbers to values on which the processor operates. The BBC/BBS instructions use big-endian bit ordering (0 is the most-significant bit) on a big-endian processor configuration. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 25 6月, 2012 1 次提交
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由 Igor Mammedov 提交于
Chains of exception handlers are currently unused feature. Dropping it to be consistent with target-i386 but it may simplify qom-ifying CPU in future like for target-i386. Signed-off-by: NIgor Mammedov <imammedo@redhat.com>
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