- 14 3月, 2015 1 次提交
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由 Richard Henderson 提交于
This is improved type checking for the translators -- it's no longer possible to accidentally swap arguments to the branch functions. Note that the code generating backends still manipulate labels as int. With notable exceptions, the scope of the change is just a few lines for each target, so it's not worth building extra machinery to do this change in per-target increments. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Cc: Michael Walle <michael@walle.cc> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Anthony Green <green@moxielogic.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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- 03 3月, 2015 5 次提交
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由 Bastian Koppelmann 提交于
Add helpers helper_addsur_h/_ssov which adds one halfword and subtracts one halfword, rounds / and saturates each half word independently. Add microcode helper functions: * gen_maddsu_h/sus_h: multiply two halfwords left justified and add to the first one word and subtract from the second one word / and saturate each resulting word independetly. * gen_maddsum_h/sums_h: multiply two halfwords in q-format left justified and add to the first one word and subtract from the second one word / and saturate each resulting word independetly. * gen_maddsur32_h/32s_h: multiply two halfwords in q-format left justified and add to the first one word and subtract from the second one word, round both results / and saturate each resulting word independetly. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
Add helpers: * madd64_q_ssov: multiply two 32 bit q-format number, add them with a 64 bit q-format number and saturate. * madd32_q_add_ssov: add two 64 bit q-format numbers and return a 32 bit result. * maddr_q_ssov: multiplay two 32 bit q-format numbers, add a 32 bit q-format number and saturate. * maddr_q: multiplay two 32 bit q-format numbers and add a 32 bit q-format number. Note: madd instructions in the q format can behave strange, e.g. 0x1 + (0x80000000 * 0x80000000) << 1 for 32 bit signed values does not cause an overflow on the guest, because all intermediate results should be handled as if they are indefinitely precise. We handle this by inverting the overflow bit for all cases: a + (0x80000000 * 0x80000000) << 1. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
Add helpers: * add64_ssov: adds two 64 bit values and saturates the result. * addr_h/_ssov: adds two halfwords with two words in q-format with rounding / and saturates each result independetly. Add microcode generator: * gen_add64_d: adds two 64 bit values. * gen_addsub64_h: adds/subtracts one halfwords with a word and adds/ subtracts another halftword with another word. * gen_madd_h/s_h: multiply four halfwords, add each result left justfied to two word values / and saturate each result. * gen_maddm_h/s_h: multiply four halfwords, add each result left justfied to two words values in q-format / and saturate each result. * gen_maddr32/64_h/s_h: multiply four halfwords, add each result left justfied to two halftwords/words values in q-format / and saturate each result. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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- 13 2月, 2015 2 次提交
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由 Richard Henderson 提交于
The method by which we count the number of ops emitted is going to change. Abstract that away into some inlines. Reviewed-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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由 Richard Henderson 提交于
Reviewed-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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- 27 1月, 2015 6 次提交
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由 Bastian Koppelmann 提交于
Add microcode generator function gen_cond_sub. Add helper functions: * ixmax/ixmin: search for the max/min value and its related index in a vector of 16-bit values. * pack: dack two data registers into an IEEE-754 single precision floating point format number. * dvadj: divide-adjust the result after dvstep instructions. * dvstep: divide a reg by a divisor, producing 8-bits of quotient at a time. OPCM_32_RRR_FLOAT -> OPCM_32_RRR_DIVIDE Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
This fixes one bug and one false positive found by coverity. The bug is, that gen_mtcr was missing a mask to check the flag, which resulted in dead code. The false positive is a intentional missing break for a jump and link address insn followed by a jump and link insn. This adds a fall through comment to avoid the false positive in the future. Reported-by: NMarkus Armbruster <armbru@redhat.com> Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
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由 Bastian Koppelmann 提交于
Fix tc1796 cpu model using wrong ISA version. Fix cond_add sometimes writing back wrong result. Fix RCR_SEL and RCR_SELN using wrong registers for result and cond. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
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- 15 1月, 2015 1 次提交
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由 Stefan Weil 提交于
adress -> address managment -> management Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: NStefan Weil <sw@weilnetz.de> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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- 03 1月, 2015 1 次提交
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NPavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 22 12月, 2014 11 次提交
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由 Bastian Koppelmann 提交于
Add instructions of RR1 opcode format, that have 0xb3 as first opcode. Add helper functions mulh, mulmh and mulrh, that compute multiplication, with multiprecision (mulmh) or rounding (mulrh) of 4 halfwords, being either low or high parts of two 32 bit regs. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
Fix gen_mtcr using wrong register. Fix gen_mtcr/mfcr using sign extended offsets. Fix B format insn using not sign extendend offsets. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
Some of the 1.6 ISA instructions were still missing. So let's add them. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
Add instructions of RR opcode format, that have 0x4b as the first opcode. Add helper functions: * parity: Calculates the parity bits for every byte of a 32 int. * bmerge/bsplit: Merges two regs into one bitwise/Splits one reg into two bitwise. * unpack: unpack a IEEE 754 single precision floating point number as exponent and mantissa. * dvinit_b_13/131: (ISA v1.3/v1.31)Prepare operands for a divide operation, where the quotient result is guaranteed to fit into 8 bit. * dvinit_h_13/131: (ISA v1.3/v1.31)Prepare operands for a divide operation, where the quotient result is guaranteed to fit into 16 bit. OPCM_32_RR_FLOAT -> OPCM_32_RR_DIVIDE. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
Add instructions of RR opcode format, that have 0x1 as the first opcode. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
Add instructions of RR opcode format, that have 0xf as the first opcode. Add helper functions: * clo/z/s: Counts leading ones/zeros/signs. * clo/z/s_h: Count leading ones/zeros/signs in two haflwords. * sh/_h: Shifts one/two word/hwords. * sha/_h: Shifts one/two word/hwords arithmeticly. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
Add instructions of RR opcode format, that have 0xb as the first opcode. Add helper functions, for hword and byte arithmetics: * add_h_ssov/suov: Add two halfword and saturate on overflow. * sub_h_ssov/suov: Sub two halfword and saturate on overflow. * absdif_h_ssov: Compute absolute difference for halfwords and saturate on overflow. * abs_h_ssov/suov: Compute absolute value for two halfwords and saturate on overflow. * abs_b/h: Compute absolute value for four/two bytes/halfwords * absdif_b/h: Compute absolute difference for four/two bytes/halfwords * add_b/h: Add four/two bytes/halfwords. * sub_b/h: Sub four/two bytes/halfwords. * eq_b/h: Compare four/two bytes/halfwords with four/two bytes/halfwords on equality and set all bits of to either one ore zero. * eqany_b/h: Compare four/two bytes/halfwords with four/two bytes/halfwords on equality. * lt_b/bu/h/hu: Compare four/two bytes/halfwords with four/two bytes/halfwords on less than signed and unsigned. * max_b/bu/h/hu: Calculate max for four/two bytes/halfwords signed and unsigned. * min_b/bu/h/hu: Calculate min for four/two bytes/halfwords signed and unsigned. Add helper function abs_ssov, that computes the absolute value for a 32 bit integer and saturates on overflow. Add microcode generator functions: * gen_sub_CC: Caluclates sub and sets the carry bit. * gen_subc_CC: Caluclates sub and carry and sets the carry bit * gen_abs: Compute absolute value for a 32 bit integer. * gen_cond_w: Compares two 32 bit values on cond and sets result either zero or all bits one. OPC2_32_RR_MIN switched with OPC2_32_RR_MIN_U. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
The mask is actually 7 bit long, instead of 6, so the expression checking for JNZ.T is always false. Let's make the mask 1 bit wider. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
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由 Alex Zuepke 提交于
Now using psw_read() to retrieve the status bits correctly. Signed-off-by: NAlex Zuepke <alexander.zuepke@hs-rm.de> Reviewed-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
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由 Alex Zuepke 提交于
Signed-off-by: NAlex Zuepke <alexander.zuepke@hs-rm.de> Reviewed-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
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由 Alex Zuepke 提交于
Signed-off-by: NAlex Zuepke <alexander.zuepke@hs-rm.de> Reviewed-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
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- 10 12月, 2014 9 次提交
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由 Bastian Koppelmann 提交于
Add instructions of RCR opcode format. Add helper for madd32/64_ssov and madd32/64_suov. Add helper for msub32/64_ssov and msub32/64_suov. Add microcode generator function madd/msub for 32bit and 64bit, which calculate a mul and a add/sub. OPC2_32_RCR_MSUB_U_32 -> OPC2_32_RCR_MSUB_U_32. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
Add instructions of RLC opcode format. Add helper psw_write/read. Add microcode generator gen_mtcr/mfcr, which loads/stores a value to a core special function register, which are defined in csfr.def Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
Add instructions of RCPW, RCRR and RCRW opcode format. Add microcode generator function gen_insert. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
Since all the TriCore instructionsets are subsets of each other (1.3 C 1.3.1 C 1.6), make the features implying each other, e.g 1.6 also has 1.3.1 and 1.3. This way we only need to check our features for the instructionset, where a instruction was first introduced. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
Add instructions of RC opcode format. Add helper for mul, sha, absdif with signed saturation on overflow. Add helper for add, sub, mul with unsigned saturation on overflow. Add microcode generator functions: * gen_add_CC, which calculates the carry bit. * gen_addc_CC, which adds the carry bit to the add and calculates the carry bit. * gen_absdif, which calculates the absolute difference. * gen_mul_i64s/u, which mul two 32 bits val into one 64bit reg. * gen_sh_hi, which shifts two 16bit words in one reg. * gen_sha_hi, which does a arithmetic shift on two 16bit words. * gen_sh_cond, which shifts left a reg by one and writes the result of cond into the lsb. * gen_accumulating_cond, which ands/ors/xors the result of cond of the lsbs with the lsb of the result. * gen_eqany_bi/hi, which checks ever byte/hword on equality. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
Add instructions of BRR opcode format. Add MASK_OP_BRR_DISP15_SEXT. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
Add instructions of BRN opcode format. Add MASK_OP_BRN_DISP15_SEXT. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
Add instructions of BRC opcode format. Fixed OP2_BRC_JGE -> OP2_32_BRC_JGE Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
Add instructions of BOL opcode format. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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- 20 10月, 2014 4 次提交
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由 Bastian Koppelmann 提交于
Add instructions of BO opcode format. Add microcode generator functions gen_swap, gen_ldmst. Add microcode generator functions gen_st/ld_preincr, which write back the address after the memory access. Add helper for circular and bit reverse addr mode calculation. Add sign extended bitmask for BO_OFF10 field. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
Add instructions of BIT opcode format. Add microcode generator functions gen_bit_1/2op to do 1/2 bit operations on the last bit. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
Add instructions of B opcode format. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Bastian Koppelmann 提交于
Add instructions of ABS, ABSB opcode format. Add microcode generator functions for ld/st of two 32bit reg as one 64bit value. Add microcode generator functions for ldmst and swap. Add helper ldlcx, lducx, stlcx and stucx. Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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