MIPS queue October 2018, part1, v2

# gpg: Signature made Thu 18 Oct 2018 19:39:00 BST
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-october-2018-part1-v2: (28 commits)
  target/mips: Add opcodes for nanoMIPS EVA instructions
  target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PH
  target/mips: Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S>
  target/mips: Implement hardware page table walker for MIPS32
  target/mips: Add reset state for PWSize and PWField registers
  target/mips: Add CP0 PWCtl register
  target/mips: Add CP0 PWSize register
  target/mips: Add CP0 PWField register
  target/mips: Add CP0 PWBase register
  target/mips: Add CP0 Config2 to DisasContext
  target/mips: Improve DSP R2/R3-related naming
  target/mips: Add availability control for DSP R3 ASE
  target/mips: Add bit definitions for DSP R3 ASE
  target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags)
  target/mips: Increase 'supported ISAs/ASEs' flag holder size
  target/mips: Add opcode values of MXU ASE
  target/mips: Add organizational chart of MXU ASE
  target/mips: Add assembler mnemonics list for MXU ASE
  target/mips: Add basic description of MXU ASE
  target/mips: Add a comment before each CP0 register section in cpu.h
  ...
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Add opcodes for nanoMIPS EVA instructions: CACHEE, LBE, LBUE, LHE,
LHUE, LLE, LLWPE, LWE, PREFE, SBE, SCE, SCWPE, SHE, SWE.
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: NDimitrije Nikolic <dnikolic@wavecomp.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Fix misplaced 'break' in handling of NM_SHRA_R_PH. Found by
Coverity (CID 1395627).
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: NStefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S> instructions.
Their handling was permuted.
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: NMatthew Fortune <matthew.fortune@mips.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Implement hardware page table walker. This implementation is
limiter only to MIPS32.
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: NYongbok Kim <yongbok.kim@mips.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Add reset state for PWSize and PWField registers. The reset state
is different for pre-R6 and R6 (and post-R6) ISAa.
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: NYongbok Kim <yongbok.kim@mips.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Add PWCtl register (CP0 Register 5, Select 6).

The PWCtl register configures hardware page table walking for TLB
refills.

This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1. It contains following
fields:

PWEn     (31)   - Hardware Page Table walker enable
PWDirExt (30)   - If 1, 4-th level implemented (MIPS64 only)
XK       (28)   - If 1, walker handles xkseg (MIPS64 only)
XS       (27)   - If 1, walker handles xsseg (MIPS64 only)
XU       (26)   - If 1, walker handles xuseg (MIPS64 only)
DPH      (7)    - Dual Page format of Huge Page support
HugePg   (6)    - Huge Page PTE supported in Directory levels
PSn      (5..0) - Bit position of PTEvld in Huge Page PTE
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: NYongbok Kim <yongbok.kim@mips.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Add PWSize register (CP0 Register 5, Select 7).

The PWSize register configures hardware page table walking for TLB
refills.

This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1. It contains following
fields:

BDW  (37..32) Base Directory index width (MIPS64 only)
GDW  (29..24) Global Directory index width
UDW  (23..18) Upper Directory index width
MDW  (17..12) Middle Directory index width
PTW  (11..6 ) Page Table index width
PTEW ( 5..0 ) Left shift applied to the Page Table index
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: NYongbok Kim <yongbok.kim@mips.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Add PWField register (CP0 Register 5, Select 6).

The PWField register configures hardware page table walking for TLB
refills.

This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1. It contains following
fields:

MIPS64:
BDI  (37..32) - Base Directory index
GDI  (29..24) - Global Directory index
UDI  (23..18) - Upper Directory index
MDI  (17..12) - Middle Directory index
PTI  (11..6 ) - Page Table index
PTEI ( 5..0 ) - Page Table Entry shift

MIPS32:
GDW  (29..24) - Global Directory index
UDW  (23..18) - Upper Directory index
MDW  (17..12) - Middle Directory index
PTW  (11..6 ) - Page Table index
PTEW ( 5..0 ) - Page Table Entry shift
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: NYongbok Kim <yongbok.kim@mips.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Add PWBase register (CP0 Register 5, Select 5).

The PWBase register contains the Page Table Base virtual address.

This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1.
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: NYongbok Kim <yongbok.kim@mips.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Add field corresponding to CP0 Config2 to DisasContext. This is
needed for availability control via Config2 bits.
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: NStefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Do following replacements:

ASE_DSPR2 -> ASE_DSP_R2
ASE_DSPR3 -> ASE_DSP_R3
MIPS_HFLAG_DSPR2 -> MIPS_HFLAG_DSP_R2
MIPS_HFLAG_DSPR3 -> MIPS_HFLAG_DSP_R3
check_dspr2() -> check_dsp_r2()
check_dspr3() -> check_dsp_r3()

and several other similar minor replacements.
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: NStefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Add infrastructure for availability control for DSP R3 ASE MIPS
instructions. Only BPOSGE32C currently belongs to DSP R3 ASE, but
this is likely to be changed in near future.
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: NStefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Add DSP R3 ASE related bit definition for insn_flags and hflags.
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: NStefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Distribute bits 56-63 vendor-specific ASEs as follows:

  - bits 0-31 MIPS base instruction sets
  - bits 32-47 MIPS ASEs
  - bits 48-55 vendor-specific base instruction sets
  - bits 56-63 vendor-specific ASEs
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Increase the size of insn_flags holder size to 64 bits. This is
needed for future extensions since existing bits are almost all used.
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Add opcode values for all instructions in MXU ASE.
Reviewed-by: NStefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Add a comment that contains an organizational chart of MXU ASE
instructions.
Reviewed-by: NStefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Add a comment that contains a list all MXU instructions,
expressed in assembler mnemonics.
Reviewed-by: NStefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Add a comment that contains a basic description of MXU ASE.
Reviewed-by: NStefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Add a comment before each CP0 register section in CPUMIPSState
definition, thus visually separating these sections.
Reviewed-by: NStefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Add a comment with an overview of CP0 registers close to the
definition of their corresponding fields in CPUMIPSState.
Reviewed-by: NStefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Add infrastructure for handling MIPS-specific prctl(). This is,
for now, just an empty placeholder. The real handling will be
implemented in subsequent patches.
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: NStefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Add MIPS-specific prctl() options TARGET_PR_SET_FP_MODE	and
TARGET_PR_SET_FP_MODE. These values are essentially copied from
linux kernel header include/uapi/linux/prctl.h.

This is done in a way consistent with a similar case of
aarch64-specific prctl() options TARGET_PR_SVE_SET_VL and
TARGET_PR_SVE_GET_VL.
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: NStefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Regarding R5900 CPU, some sources indicate that the Emotion Engine
ISA/ASE was designed by Toshiba and licensed to Sony. Others sources
claim it was a joint effort. It therefore makes sense to refer to
the CPU as "Toshiba/Sony R5900".

Also, remove and "'s" in the line for some other CPU, for the sake
of consistency.
Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Reported-by: NMaciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: NFredrik Noring <noring@nocrew.org>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Add Mips_elf_abiflags_v0 structure to elf.h. The source of information
is kernel header arch/mips/include/asm/elf.h.
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: NStefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Add MIPS_ABI_FP_XXX constants to elf.h. The source of information
is kernel header arch/mips/include/asm/elf.h.
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: NStefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Fix existing and add missing PT_MIPS_XXX constants in elf.h.
This is copied from kernel header arch/mips/include/asm/elf.h.
Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: NStefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

Yongbok Kim used two email adresses for QEMU contributions -
his company changed its ownership/name.
Reviewed-by: NStefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>

- Updates for qtest entries in test/Makefile.include
- Simple updates for some shell scripts
- Misc simple patches for files without regular subsystem pull requests

# gpg: Signature made Wed 17 Oct 2018 08:20:35 BST
# gpg:                using RSA key 2ED9D774FE702DB5
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>"
# gpg:                 aka "Thomas Huth <thuth@redhat.com>"
# gpg:                 aka "Thomas Huth <huth@tuxfamily.org>"
# gpg:                 aka "Thomas Huth <th.huth@posteo.de>"
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3  EAB9 2ED9 D774 FE70 2DB5

* remotes/huth-gitlab/tags/pull-request-2018-10-17:
  configure: remove glib_subprocess check
  hw/core/generic-loader: Compile only once, not for each target
  cpu: Provide a proper prototype for target_words_bigendian() in a header
  hw/core/generic-loader: Set a category for the generic-loader device
  qemu/compiler: Wrap __attribute__((flatten)) in a macro
  mailmap: Fix Reimar Döffinger name
  show-fixed-bugs.sh: Modern shell scripting (use $() instead of ``)
  git-submodule.sh: Modern shell scripting (use $() instead of ``)
  archive-source.sh: Modern shell scripting (use $() instead of ``)
  MAINTAINERS: update block/sheepdog maintainers
  gdbstub: Remove unused include
  tests: remove gcov-files- variables
  tests: Prevent more accidental test disabling
  target/cris/translate: Get rid of qemu_log_separate()
  qemu-common.h: update copyright date to 2018
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Queued hppa patch

# gpg: Signature made Tue 16 Oct 2018 23:45:46 BST
# gpg:                using RSA key 64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-hppa-20181016:
  target/hppa: Raise exception 26 on emulated hardware
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

This should have been removed as part of commit
692fbdf9.
Signed-off-by: NMarc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: NThomas Huth <thuth@redhat.com>
Signed-off-by: NThomas Huth <thuth@redhat.com>

The generic-loader is currently compiled target specific due to one
single "#ifdef TARGET_WORDS_BIGENDIAN" in the file. We have already a
function called target_words_bigendian() for this instead, so we can
put the generic-loader into common-obj to save some compilation time.
Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: NPhilippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: NLaszlo Ersek <lersek@redhat.com>
Reviewed-by: NAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: NThomas Huth <thuth@redhat.com>

We've got three places already that provide a prototype for this
function in a .c file - that's ugly. Let's provide a proper prototype
in a header instead, with a proper description why this function should
not be used in most cases.
Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: NLaszlo Ersek <lersek@redhat.com>
Signed-off-by: NThomas Huth <thuth@redhat.com>

Each device that is instantiatable by the users should be marked with
a category. Since the generic-loader does not fit anywhere else, put
it into the MISC category.
Reviewed-by: NAlistair Francis <alistair.francis@wdc.com>
Reviewed-by: NCornelia Huck <cohuck@redhat.com>
Signed-off-by: NThomas Huth <thuth@redhat.com>

Older versions of Clang (before 3.5) and GCC (before 4.1) do not
support the "__attribute__((flatten))" yet. We don't care about
such old versions of GCC anymore, but since Clang 3.4 is still
used in EPEL for RHEL7 / CentOS 7, we should not use this attribute
directly but with a wrapper macro instead.
Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: NThomas Huth <thuth@redhat.com>

This probably happened when interpreting the utf8 name as latin1.

Fixes dbbaaff6 and f4e94dfe.
Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: NThomas Huth <thuth@redhat.com>

On PCXS chips (PA7000, pa 1.1a), trap #18 is raised on memory faults,
while all later chips (>= PA7100) generate either trap #26, #27 or #28
(depending on the fault type).

Since the current qemu emulation emulates a B160L machine (with a
PA7300LC PCX-L2 chip, we should raise trap #26 (EXCP_DMAR) instead
of #18 (EXCP_DMP) on access faults by the Linux kernel to page zero.

With the patch we now get the correct output (I tested against real
hardware):
 Kernel Fault: Code=26 (Data memory access rights trap)
instead of:
 Kernel Fault: Code=18 (Data memory protection/unaligned access trap)
Signed-off-by: NHelge Deller <deller@gmx.de>
Message-Id: <20181007205153.GA30270@ls3530.fritz.box>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

target-arm queue:
 * hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
 * target/arm: Fix aarch64_sve_change_el wrt EL0
 * target/arm: Define fields of ISAR registers
 * target/arm: Align cortex-r5 id_isar0
 * target/arm: Fix cortex-a7 id_isar0
 * net/cadence_gem: Fix various bugs, add support for new
   features that will be used by the Xilinx Versal board
 * target-arm: powerctl: Enable HVC when starting CPUs to EL2
 * target/arm: Add the Cortex-A72
 * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
 * target/arm: Mask PMOVSR writes based on supported counters
 * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
 * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls

# gpg: Signature made Tue 16 Oct 2018 17:42:01 BST
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20181016-1:
  coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
  target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
  target/arm: Mask PMOVSR writes based on supported counters
  target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
  target/arm: Add the Cortex-A72
  target-arm: powerctl: Enable HVC when starting CPUs to EL2
  net: cadence_gem: Implement support for 64bit descriptor addresses
  net: cadence_gem: Add support for selecting the DMA MemoryRegion
  net: cadence_gem: Add support for extended descriptors
  net: cadence_gem: Add macro with max number of descriptor words
  net: cadence_gem: Use uint32_t for 32bit descriptor words
  net: cadence_gem: Disable TSU feature bit
  target/arm: Fix cortex-a7 id_isar0
  target/arm: Align cortex-r5 id_isar0
  target/arm: Define fields of ISAR registers
  target/arm: Fix aarch64_sve_change_el wrt EL0
  hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Various shell files contain a mix between obsolete ``
and modern $(); It would be nice to convert to using $()
everywhere.
Signed-off-by: NMao Zhongyi <maozhongyi@cmss.chinamobile.com>
Reviewed-by: NThomas Huth <thuth@redhat.com>
Signed-off-by: NThomas Huth <thuth@redhat.com>