- 21 5月, 2019 4 次提交
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由 Christian Borntraeger 提交于
Provide the "Miscellaneous-Instruction-Extensions Facility 3" via stfle.61. Signed-off-by: NChristian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20190429090250.7648-4-borntraeger@de.ibm.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 Christian Borntraeger 提交于
csske will be removed in a future machine. Ignore it for expanding the cpu model. Otherwise qemu falls back to z9. Signed-off-by: NChristian Borntraeger <borntraeger@de.ibm.com> Cc: qemu-stable@nongnu.org Reviewed-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20190429090250.7648-3-borntraeger@de.ibm.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 Cornelia Huck 提交于
commit a188339ca5a396acc588e5851ed7e19f66b0ebd9 Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 Cornelia Huck 提交于
We need to copy sve_context.h for aarch64. Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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- 17 5月, 2019 36 次提交
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由 Cornelia Huck 提交于
Implement all Vector Integer Instructions introduced with the "Vector Facility" for s390x TCG. # gpg: Signature made Fri 17 May 2019 01:37:40 PM CEST # gpg: using RSA key 4DDE10F700FF835A # gpg: Good signature from "David Hildenbrand <david@redhat.com>" [full] # gpg: aka "David Hildenbrand <davidhildenbrand@gmail.com>" [full] * tag 's390x-tcg-2019-05-17-2': (40 commits) s390x/tcg: Implement VECTOR TEST UNDER MASK s390x/tcg: Implement VECTOR SUM ACROSS WORD s390x/tcg: Implement VECTOR SUM ACROSS QUADWORD s390x/tcg: Implement VECTOR SUM ACROSS DOUBLEWORD s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW INDICATION s390x/tcg: Implement VECTOR SUBTRACT COMPUTE BORROW INDICATION s390x/tcg: Implement VECTOR SUBTRACT s390x/tcg: Implement VECTOR SHIFT RIGHT LOGICAL * s390x/tcg: Implement VECTOR SHIFT RIGHT ARITHMETIC s390x/tcg: Implement VECTOR SHIFT LEFT DOUBLE BY BYTE s390x/tcg: Implement VECTOR SHIFT LEFT (BY BYTE) s390x/tcg: Implement VECTOR ELEMENT SHIFT s390x/tcg: Implement VECTOR ELEMENT ROTATE AND INSERT UNDER MASK s390x/tcg: Implement VECTOR ELEMENT ROTATE LEFT LOGICAL s390x/tcg: Implement VECTOR POPULATION COUNT s390x/tcg: Implement VECTOR OR WITH COMPLEMENT s390x/tcg: Implement VECTOR OR s390x/tcg: Implement VECTOR NOT EXCLUSIVE OR s390x/tcg: Implement VECTOR NOR ... Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
Let's return the cc value directly via cpu_env. Unfortunately there isn't a simple way to calculate the value lazily - one would have to calculate and store e.g. the population count of the mask and the result so it can be evaluated in a cc helper. But as VTM only sets the cc, we can assume the value will be needed soon either way. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Similar to VECTOR SUM ACROSS DOUBLEWORD. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Similar to VECTOR SUM ACROSS DOUBLEWORD, however without a loop and using 128-bit calculations. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Perform the calculations without a helper. Only 16 bit or 32 bit values have to be added. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Mostly courtesy of Richard H. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Fairly easy as only 128-bit handling is required. Simply perform the subtraction and then subtract the borrow. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Let's keep it simple for now and handle 8/16 bit elements via helpers. Especially for 8/16, we could come up with some bit tricks. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
We can use tcg_gen_sub2_i64() to do 128-bit subtraction and otherwise existing gvec helpers. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Similar to VECTOR SHIFT RIGHT ARITHMETICAL. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Similar to VECTOR SHIFT LEFT ARITHMETIC. Add s390_vec_sar() similar to s390_vec_shr(). Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Inline expansion courtesy of Richard H. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
We can reuse the existing 128-bit shift utility function. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
We can use all the fancy new vector helpers implemented by Richard. One important thing to take care of is always to properly mask of unused bits from the shift count. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Use the new vector expansion for GVecGen3i. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Take care of properly taking the modulo of the count. We might later want to come back and create a variant of VERLL where the base register is 0, resulting in an immediate. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Similar to VECTOR COUNT TRAILING ZEROES. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Again, vector enhancements facility 1 material. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Reuse a gvec helper. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Again, part of vector enhancement facility 1. The operation corresponds to an bitwise equality check. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Part of vector enhancements facility 1, but easy to implement. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Yet another set of variants. Implement it similar to VECTOR MULTIPLY AND ADD *. At least for one variant we have a gvec helper we can reuse. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Quite some variants to handle. At least handle some 32-bit element variants via gvec expansion (we could also handle 16/32-bit variants for ODD and EVEN easily via gvec expansion, but let's keep it simple for now). Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Luckily, we already have gvec helpers for all four cases. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Similar to VECTOR LOAD COMPLEMENT. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
We can reuse an existing gvec helper for negating the values. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
A galois field multiplication in field 2 is like binary multiplication, however instead of doing ordinary binary additions, xor's are performed. So no carries are considered. Implement all variants via helpers. s390_vec_sar() and s390_vec_shr() will be reused later on. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Easy, we can reuse an existing gvec helper. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Implement it similar to VECTOR COUNT LEADING ZEROS. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
For 8/16, use the 32 bit variant and properly subtract the added leading zero bits. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
To carry out the comparison, we can reuse the existing gvec comparison function. In case the CC is to be computed, save the result vector and compute the CC lazily. The result is a vector consisting of all 1's for elements that matched and 0's for elements that didn't match. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Fairly easy to implement, we can make use of the existing CC helpers cmps64 and cmpu64 - we siply have to sign extend the elements. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Time to introduce read_vec_element_i32 and write_vec_element_i32. Take proper care of properly adding the carry. We can perform both additions including the carry via tcg_gen_add2_i32(). Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Similar to VECTOR AVERAGE but without sign extension. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Handle 32/64-bit elements via gvec expansion and the 8/16 bits via ool helpers. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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