- 04 2月, 2019 1 次提交
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由 Anthony PERARD 提交于
Its last uses was removed by: 6d7c06c2 "Remove broken Xen PV domain builder". Signed-off-by: NAnthony PERARD <anthony.perard@citrix.com> Reviewed-by: NPaul Durrant <paul.durrant@citrix.com>
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- 02 2月, 2019 2 次提交
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由 Peter Maydell 提交于
Block layer patches: - vmdk: Support for blockdev-create - block: Apply auto-read-only for ro-whitelist drivers - virtio-scsi: Fixes related to attaching/detaching iothreads - scsi-disk: Fixed erroneously detected multipath setup with multiple disks created with node-names. Added device_id property. - block: Fix hangs in synchronous APIs with iothreads - block: Fix invalidate_cache error path for parent activation - block-backend, mirror, qcow2, vpc, vdi, qemu-iotests: Minor fixes and code improvements # gpg: Signature made Fri 01 Feb 2019 15:23:10 GMT # gpg: using RSA key 7F09B272C88F2FD6 # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full] # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * remotes/kevin/tags/for-upstream: (27 commits) scsi-disk: Add device_id property scsi-disk: Don't use empty string as device id qtest.py: Wait for the result of qtest commands block: Fix invalidate_cache error path for parent activation iotests/236: fix transaction kwarg order iotests: Filter second BLOCK_JOB_ERROR from 229 virtio-scsi: Forbid devices with different iothreads sharing a blockdev scsi-disk: Acquire the AioContext in scsi_*_realize() virtio-scsi: Move BlockBackend back to the main AioContext on unplug block: Eliminate the S_1KiB, S_2KiB, ... macros block: Remove blk_attach_dev_legacy() / legacy_dev code block: Apply auto-read-only for ro-whitelist drivers uuid: Make qemu_uuid_bswap() take and return a QemuUUID block/vdi: Don't take address of fields in packed structs block/vpc: Don't take address of fields in packed structs vmdk: Reject excess extents in blockdev-create iotests: Add VMDK tests for blockdev-create iotests: Filter cid numbers in VMDK extent info vmdk: Implement .bdrv_co_create callback vmdk: Refactor vmdk_create_extent ... Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
target-arm queue: * New machine mps2-an521 -- this is a model of the AN521 FPGA image for the MPS2 devboard * Fix various places where we failed to UNDEF invalid A64 instructions * Don't UNDEF a valid FCMLA on 32-bit inputs * Fix some bugs in the newly-added PAuth implementation * microbit: Implement NVMC non-volatile memory controller # gpg: Signature made Fri 01 Feb 2019 16:06:03 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190201: (47 commits) tests/microbit-test: Add tests for nRF51 NVMC arm: Instantiate NRF51 special NVM's and NVMC hw/nvram/nrf51_nvm: Add nRF51 non-volatile memories target/arm: fix decoding of B{,L}RA{A,B} target/arm: fix AArch64 virtual address space size linux-user: Initialize aarch64 pac keys aarch64-linux-user: Enable HWCAP bits for PAuth aarch64-linux-user: Update HWCAP bits from linux 5.0-rc1 target/arm: Always enable pac keys for user-only arm: Clarify the logic of set_pc() target/arm: Enable API, APK bits in SCR, HCR target/arm: Add a timer to predict PMU counter overflow target/arm: Send interrupts on PMU counter overflow target/arm/translate-a64: Fix mishandling of size in FCMLA decode target/arm/translate-a64: Fix FCMLA decoding error exec.c: Don't reallocate IOMMUNotifiers that are in use target/arm/translate-a64: Don't underdecode SDOT and UDOT target/arm/translate-a64: Don't underdecode FP insns target/arm/translate-a64: Don't underdecode add/sub extended register target/arm/translate-a64: Don't underdecode SIMD ld/st single ... Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 01 2月, 2019 37 次提交
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由 Steffen Görtz 提交于
Signed-off-by: NSteffen Görtz <contrib@steffen-goertz.de> Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com> Acked-by: NThomas Huth <thuth@redhat.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20190201023357.22596-4-stefanha@redhat.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Steffen Görtz 提交于
Instantiates UICR, FICR, FLASH and NVMC in nRF51 SOC. Signed-off-by: NSteffen Görtz <contrib@steffen-goertz.de> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NStefan Hajnoczi <stefanha@redhat.com> Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com> Message-id: 20190201023357.22596-3-stefanha@redhat.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Steffen Görtz 提交于
The nRF51 contains three regions of non-volatile memory (NVM): - CODE (R/W): contains code - FICR (R): Factory information like code size, chip id etc. - UICR (R/W): Changeable configuration data. Lock bits, Code protection configuration, Bootloader address, Nordic SoftRadio configuration, Firmware configuration. Read and write access to the memories is managed by the Non-volatile memory controller. Memory schema: [ CPU ] -+- [ NVM, either FICR, UICR or CODE ] | | \- [ NVMC ] Signed-off-by: NSteffen Görtz <contrib@steffen-goertz.de> Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com> Tested-by: NJoel Stanley <joel@jms.id.au> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20190201023357.22596-2-stefanha@redhat.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Remi Denis-Courmont 提交于
A flawed test lead to the instructions always being treated as unallocated encodings. Fixes: https://bugs.launchpad.net/bugs/1813460Signed-off-by: NRemi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Remi Denis-Courmont 提交于
Since QEMU does not support the ARMv8.2-LVA, Large Virtual Address, extension (yet), the VA address space is 48-bits plus a sign bit. User mode can only handle the positive half of the address space, so that makes a limit of 48 bits. (With LVA, it would be 53 and 52 bits respectively.) The incorrectly large address space conflicts with PAuth instructions, which use bits 48-54 and 56-63 for the pointer authentication code. This also conflicts with (as yet unsupported by QEMU) data tagging and with the ARMv8.5-MTE extension. Signed-off-by: NRemi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Initialize the keys to a non-zero value on process start. Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NLaurent Vivier <laurent@vivier.eu> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Drop the pac properties. This approach cannot work as written because the properties are applied before arm_cpu_reset, which zeros SCTLR_EL1 (amongst everything else). We can re-introduce the properties if they turn out to be useful. But since linux 5.0 enables all of the keys, they may not be. Fixes: 1ae9cfbdSigned-off-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Julia Suvorova 提交于
Until now, the set_pc logic was unclear, which raised questions about whether it should be used directly, applying a value to PC or adding additional checks, for example, set the Thumb bit in Arm cpu. Let's set the set_pc logic for “Configure the PC, as was done in the ELF file” and implement synchronize_with_tb hook for preserving PC to cpu_tb_exec. Signed-off-by: NJulia Suvorova <jusual@mail.ru> Acked-by: NStefan Hajnoczi <stefanha@redhat.com> Message-id: 20190129121817.7109-1-jusual@mail.ru Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
These bits become writable with the ARMv8.3-PAuth extension. Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190129143511.12311-1-richard.henderson@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Aaron Lindsay OS 提交于
Make PMU overflow interrupts more accurate by using a timer to predict when they will overflow rather than waiting for an event to occur which allows us to otherwise check them. Signed-off-by: NAaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190124162401.5111-3-aaron@os.amperecomputing.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Aaron Lindsay OS 提交于
Whenever we notice that a counter overflow has occurred, send an interrupt. This is made more reliable with the addition of a timer in a follow-on commit. Signed-off-by: NAaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190124162401.5111-2-aaron@os.amperecomputing.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
In disas_simd_indexed(), for the case of "complex fp", each indexable element is a complex pair, so the total size is twice that indicated in the 'size' field in the encoding. We were trying to do this "double the size" operation with a left shift by 1, but this is incorrect because the 'size' field is a MO_8/MO_16/MO_32/MO_64 value, and doubling the size should be done by a simple increment. This meant we were mishandling FCMLA (by element) of values where the real and imaginary parts are 32-bit floats, and would incorrectly UNDEF this encoding. (No other insns take this code path, and for 16-bit floats it happens that 1 << 1 and 1 + 1 are both the same). Reported-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190129140411.682-3-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The FCMLA (by element) instruction exists in the "vector x indexed element" encoding group, but not in the "scalar x indexed element" group. Correctly UNDEF the unallocated encodings. Reported-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190129140411.682-2-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The tcg_register_iommu_notifier() code has a GArray of TCGIOMMUNotifier structs which it has registered by passing memory_region_register_iommu_notifier() a pointer to the embedded IOMMUNotifier field. Unfortunately, if we need to enlarge the array via g_array_set_size() this can cause a realloc(), which invalidates the pointer that memory_region_register_iommu_notifier() put into the MemoryRegion's iommu_notify list. This can result in segfaults. Switch the GArray to holding pointers to the TCGIOMMUNotifier structs, so that we can individually allocate and free them. Cc: qemu-stable@nongnu.org Fixes: 1f871c5e ("exec.c: Handle IOMMUs in address_space_translate_for_iotlb()") Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190128174241.5860-1-peter.maydell@linaro.org
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由 Peter Maydell 提交于
In the AdvSIMD scalar x indexed element and vector x indexed element encoding group, the SDOT and UDOT instructions are vector only, and their opcode is unallocated in the scalar group. Correctly UNDEF this unallocated encoding. Reported-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190125182626.9221-8-peter.maydell@linaro.org
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由 Peter Maydell 提交于
In the encoding groups * floating-point data-processing (1 source) * floating-point data-processing (2 source) * floating-point data-processing (3 source) * floating-point immediate * floating-point compare * floating-ponit conditional compare * floating-point conditional select bit 31 is M and bit 29 is S (and bit 30 is 0, already checked at this point in the decode). None of these groups allocate any encoding for M=1 or S=1. We checked this in disas_fp_compare(), disas_fp_ccomp() and disas_fp_csel(), but missed it in disas_fp_1src(), disas_fp_2src(), disas_fp_3src() and disas_fp_imm(). We also missed that in the fp immediate encoding the imm5 field must be all zeroes. Correctly UNDEF the unallocated encodings here. Reported-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190125182626.9221-7-peter.maydell@linaro.org
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由 Peter Maydell 提交于
In the "add/subtract (extended register)" encoding group, the "opt" field in bits [23:22] must be zero. Correctly UNDEF the unallocated encodings where this field is not zero. Reported-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190125182626.9221-6-peter.maydell@linaro.org
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由 Peter Maydell 提交于
In the AdvSIMD load/store single structure encodings, the non-post-indexed case should have zeroes in [20:16] (which is the Rm field for the post-indexed case). Bit 31 must also be zero (a check we got right in ldst_multiple but not here). Correctly UNDEF these unallocated encodings. Reported-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190125182626.9221-5-peter.maydell@linaro.org
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由 Peter Maydell 提交于
In the AdvSIMD load/store multiple structures encodings, the non-post-indexed case should have zeroes in [20:16] (which is the Rm field for the post-indexed case). Correctly UNDEF the currently unallocated encodings which have non-zeroes in those bits. Reported-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190125182626.9221-4-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The PRFM prefetch insn in the load/store with imm9 encodings requires idx field 0b00; we were underdecoding this by only checking !is_unpriv (which is equivalent to idx != 2). Correctly UNDEF the unallocated encodings where idx == 0b01 and 0b11 as well as 0b10. Reported-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190125182626.9221-3-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The "system instructions" and "system register move" subcategories of "branches, exception generating and system instructions" for A64 only apply if bits [23:22] are zero; other values are currently unallocated. Correctly UNDEF these unallocated encodings. Reported-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190125182626.9221-2-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Add a model of the MPS2 FPGA image described in Application Note AN521. This is identical to the AN505 image, except that it uses the SSE-200 rather than the IoTKit and so has two Cortex-M33 CPUs. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-24-peter.maydell@linaro.org
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由 Peter Maydell 提交于
In preparation for adding support for the AN521 MPS2 image, we need to handle wiring up the MPS2 device interrupt lines to both CPUs in the SSE-200, rather than just the one that the IoTKit has. Abstract out a "connect to the IoTKit interrupt line" function and make it connect to a splitter which feeds both sets of inputs for the SSE-200 case. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-23-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Add a model of the SSE-200, now we have put in all the code that lets us make it different from the IoTKit. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-22-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Instantiate a copy of the CPU_IDENTITY register block for each CPU in an SSE-200. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-21-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The SSE-200 has a CPU_IDENTITY register block, which is a set of read-only registers. As well as the usual PID/CID registers, there is a single CPUID register which indicates whether the CPU is CPU 0 or CPU 1. Implement a model of this register block. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-20-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The SSE-200 has a "CPU local security control" register bank; add an unimplemented-device stub for it. (The register bank has only one interesting register, which allows the guest to lock down changes to various CPU registers so they cannot be modified further. We don't support that in our Cortex-M33 model anyway.) Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-19-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The SSE-200 gives each CPU a register bank to use to control its L1 instruction cache. Put in an unimplemented-device stub for this. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-18-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Add unimplemented-device stubs for the various Power Policy Unit devices that the SSE-200 has. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-17-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The SSE-200 has two Message Handling Units (MHUs), which sit behind the APB PPC0. Wire up some unimplemented-device stubs for these, since we don't yet implement a real model of this device. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-16-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The SYS_VERSION and SYS_CONFIG register values differ between the IoTKit and SSE-200. Make them configurable via QOM properties rather than hard-coded, and set them appropriately in the ARMSSE code that instantiates the IOTKIT_SYSINFO device. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-15-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Create a cluster object to hold each CPU in the SSE. They are logically distinct and may be configured differently (for instance one may not have an FPU where the other does). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-14-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Give each CPU its own container memory region. This is necessary for two reasons: * some devices are instantiated one per CPU and the CPU sees only its own device * since a memory region can only be put into one container, we must give each armv7m object a different MemoryRegion as its 'memory' property, or a dual-CPU configuration will assert on realize when the second armv7m object tries to put the MR into a container when it is already in the first armv7m object's container Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-13-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The SSE-200 has two Cortex-M33 CPUs. These see the same view of memory, with the exception of the "private CPU region" which has per-CPU devices. Internal device interrupts for SSE-200 devices are mostly wired up to both CPUs, with the exception of a few per-CPU devices. External GPIO inputs on the SSE-200 device are provided for the second CPU's interrupts above 32, as is already the case for the first CPU. Refactor the code to support creation of multiple CPUs. For the moment we leave all CPUs with the same view of memory: this will not work in the multiple-CPU case, but we will fix this in the following commit. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-12-peter.maydell@linaro.org
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由 Peter Maydell 提交于
For the IoTKit the SRAM bank size is always 32K (15 bits); for the SSE-200 this is a configurable parameter, which defaults to 32K but can be changed when it is built into a particular SoC. For instance the Musca-B1 board sets it to 128K (17 bits). Make the bank size a QOM property. We follow the SSE-200 hardware in naming the parameter SRAM_ADDR_WIDTH, which specifies the number of address bits of a single SRAM bank. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-11-peter.maydell@linaro.org
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