tcg/mips/tcg-target.h defines various operations conditionally depending
upon the isa revision, however these operations are included in
mips_op_defs[] unconditionally resulting in the following runtime errors
if CONFIG_DEBUG_TCG is defined:

Invalid op definition for movcond_i32
Invalid op definition for rotl_i32
Invalid op definition for rotr_i32
Invalid op definition for deposit_i32
Invalid op definition for bswap16_i32
Invalid op definition for bswap32_i32
tcg/tcg.c:1196: tcg fatal error

Fix with ifdefs like the i386 backend does for movcond_i32.
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Richard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

The definition of macro BIT in tci/tcg-target.c now conflicts with the
definition of the same macro in includes qemu/bitops.h.

This conflict was triggered by a recent change in the include chain of
tcg.c (probably commit 949fc823).
Signed-off-by: NStefan Weil <sw@weilnetz.de>
Message-id: 1375216883-23969-1-git-send-email-sw@weilnetz.de
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>

Supports CONFIG_QEMU_LDST_OPTIMIZATION
Signed-off-by: NJani Kokkonen <jani.kokkonen@huawei.com>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Reviewed-by: NClaudio Fontana <claudio.fontana@huawei.com>

Allows unwinding past the code_gen_buffer.
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

We can check the condition at compile time, rather than run time.
Reviewed-by: NAndreas Färber <afaerber@suse.de>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

These will necessarily be the same layout for all hosts.  This limits
the amount of boilerplate required to implement jit debug for a host.
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

I don't think the debugger actually looks at this for anything,
using the correct .debug_frame contents, but might as well get
it all correct.
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

With this we can generate armv7 insns even when the OS compiles for a
lower common denominator.  The macros are arranged so that when we do
compile for a given ISA, all of the runtime checks for that ISA are
optimized away.
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

GCC 4.8 defines a handy __ARM_ARCH symbol that we can use, which
will make us nicely forward compatible with ARMv8 AArch32.
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

As it really controls the availability of a thumb interworking
instruction on armv5t.
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

We can now detect and use divide instructions at runtime, rather than
having to restrict their availability to compile-time.
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

Expand the definition of "not present" to include "should not be present".
This means we can simplify the logic surrounding the generic tcg opcodes
for which the host backend ought not be providing definitions.
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

This allows TCG_TARGET_HAS_* to be a variable rather than a constant,
which allows easier support for differing ISA levels for the host.
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

Reviewed-by: NAndreas Färber <afaerber@suse.de>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

Reviewed-by: NAndreas Färber <afaerber@suse.de>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

There are several hosts with only a "div" insn.  Remainder is computed
manually from the quotient and inputs.  We can do this generically.
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

implement the 12bit scaled unsigned immediate offset
variant of LDR/STR. This improves code size by avoiding
the movi + ldst_r for naturally aligned offsets in range.
Signed-off-by: NClaudio Fontana <claudio.fontana@huawei.com>
Reviewed-by: NRichard Henderson <rth@twiddle.net>

rotr_i32 calculates the amount to left shift and puts it into a
temporary, but then doesn't use it when doing the shift.

Cc: qemu-stable@nongnu.org
Signed-off-by: NAnton Blanchard <anton@samba.org>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

add2_i64 was adding the lower double word to the upper double word
of each input. Fix this so we add the lower double words, then the
upper double words with carry propagation.

Cc: qemu-stable@nongnu.org
Signed-off-by: NAnton Blanchard <anton@samba.org>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

If our input and output is in the same register, bswap64 tries to
undo a rotate of the input. This just ends up rotating the output.

Cc: qemu-stable@nongnu.org
Signed-off-by: NAnton Blanchard <anton@samba.org>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

The rldcl instruction doesn't have an sh field, so the minor opcode
is shifted 1 bit. We were using the XO30 macro which shifted the
minor opcode 2 bits.

Remove XO30 and add MD30 and MDS30 macros which match the
Power ISA categories.

Cc: qemu-stable@nongnu.org
Signed-off-by: NAnton Blanchard <anton@samba.org>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

also put aarch64 in the list of archs that do not need an ldscript.
Signed-off-by: NJani Kokkoken <jani.kokkonen@huawei.com>
Signed-off-by: NClaudio Fontana <claudio.fontana@huawei.com>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 51AF40EE.1000104@huawei.com
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

implement the optional sign/zero extend operations with the dedicated
aarch64 instructions.
Signed-off-by: NClaudio Fontana <claudio.fontana@huawei.com>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Message-id: 51AC9A58.40502@huawei.com
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

implement the optional byte swap operations with the dedicated
aarch64 instructions.
Signed-off-by: NClaudio Fontana <claudio.fontana@huawei.com>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Message-id: 51AC9A33.9050003@huawei.com
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

add functions to AND/TEST registers with immediate patterns.
Signed-off-by: NClaudio Fontana <claudio.fontana@huawei.com>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Message-id: 51AC9A0C.3090303@huawei.com
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

for arith operations, add SUBS, ANDS, ADDS and add a shift parameter
so that all arith instructions can make use of shifted registers.
Signed-off-by: NClaudio Fontana <claudio.fontana@huawei.com>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Message-id: 51AC998B.7070506@huawei.com
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

add preliminary support for TCG target aarch64.
Signed-off-by: NClaudio Fontana <claudio.fontana@huawei.com>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 51A5C596.3090108@huawei.com
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

We've got a compile-time check for the condition in exec/cpu-defs.h.
Reviewed-by: NAndreas Färber <afaerber@suse.de>
Reviewed-by: Nliguang <lig.fnst@cn.fujitsu.com>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

When setcond2 is rewritten into setcond, the state of the destination
temp should be reset, so that a copy of the previous value is not
used instead of the result.
Reported-by: NMichael Tokarev <mjt@tls.msk.ru>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Avoid the mini constant pool for armv7, and avoid replicating
the test for pre-v7.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Found by inspection, since the effect of the bug was simply to
send all memory ops through the slow path.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Branches within a TB will always be within 16MB.
Signed-off-by: NRichard Henderson <rth@twiddle.net>

Move the slow path out of line, as the TODO's mention.
This allows the fast path to be unconditional, which can
speed up the fast path as well, depending on the core.
Signed-off-by: NRichard Henderson <rth@twiddle.net>

Work better with branch predition when we have movw+movt,
as the size of the code is the same.  Perhaps re-evaluate
when we have a proper constant pool.
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

After the previous patch, 's' and 'S' are the same.
Signed-off-by: NRichard Henderson <rth@twiddle.net>

The schedule was fully serial, with no possibility for dual issue.
The old schedule had a minimal issue of 7 cycles; the new schedule
has a minimal issue of 5 cycles.
Signed-off-by: NRichard Henderson <rth@twiddle.net>

Share code between qemu_ld and qemu_st to process the tlb.
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

Use even more primitive helper functions to avoid lots of duplicated code.
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

Make the code more readable by only having one copy of the magic
numbers, swapping registers as needed prior to that.  Speed the
compiler by not applying the rd == rn avoidance for v6 or later.
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NRichard Henderson <rth@twiddle.net>