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  1. 19 7月, 2013 3 次提交
  3. 18 7月, 2013 5 次提交
  5. 17 7月, 2013 5 次提交
  7. 16 7月, 2013 19 次提交
    • L
      qapi: qapi-commands: fix possible leaks on visitor dealloc · 8f91ad8a
      由 Luiz Capitulino 提交于 
      In qmp-marshal.c the dealloc visitor calls use the same errp
pointer of the input visitor calls. This means that if any of
the input visitor calls fails, then the dealloc visitor will
return early, before freeing the object's memory.

Here's an example, consider this code:

int qmp_marshal_input_block_passwd(Monitor *mon, const QDict *qdict, QObject **ret)
{
	[...]

    char * device = NULL;
    char * password = NULL;

    mi = qmp_input_visitor_new_strict(QOBJECT(args));
    v = qmp_input_get_visitor(mi);
    visit_type_str(v, &device, "device", errp);
    visit_type_str(v, &password, "password", errp);
    qmp_input_visitor_cleanup(mi);

    if (error_is_set(errp)) {
        goto out;
    }
    qmp_block_passwd(device, password, errp);

out:
    md = qapi_dealloc_visitor_new();
    v = qapi_dealloc_get_visitor(md);
    visit_type_str(v, &device, "device", errp);
    visit_type_str(v, &password, "password", errp);
    qapi_dealloc_visitor_cleanup(md);

	[...]

    return 0;
}

Consider errp != NULL when the out label is reached, we're going
to leak device and password.

This patch fixes this by always passing errp=NULL for dealloc
visitors, meaning that we always try to free them regardless of
any previous failure. The above example would then be:

out:
    md = qapi_dealloc_visitor_new();
    v = qapi_dealloc_get_visitor(md);
    visit_type_str(v, &device, "device", NULL);
    visit_type_str(v, &password, "password", NULL);
    qapi_dealloc_visitor_cleanup(md);
Signed-off-by: NLuiz Capitulino <lcapitulino@redhat.com>
Reviewed-by: NLaszlo Ersek <lersek@redhat.com>
Reviewed-by: NMichael Roth <mdroth@linux.vnet.ibm.com>
      8f91ad8a
    • V
      vfio: QEMU-AER: Qemu changes to support AER for VFIO-PCI devices · 7b4b0e9e
      由 Vijay Mohan Pandarathil 提交于 
      Add support for error containment when a VFIO device assigned to a KVM
guest encounters an error. This is for PCIe devices/drivers that support AER
functionality. When the host OS is notified of an error in a device either
through the firmware first approach or through an interrupt handled by the AER
root port driver, the error handler registered by the vfio-pci driver gets
invoked. The qemu process is signaled through an eventfd registered per
VFIO device by the qemu process. In the eventfd handler, qemu decides on
what action to take. In this implementation, guest is brought down to
contain the error.

The kernel patches for the above functionality has been already accepted.

This is a refresh of the QEMU patch which was reviewed earlier.
http://marc.info/?l=linux-kernel&m=136281557608087&w=2
This patch has the same contents and has been built after refreshing
to latest upstream and after the linux headers have been updated in qemu.

	- Create eventfd per vfio device assigned to a guest and register an
          event handler

	- This fd is passed to the vfio_pci driver through the SET_IRQ ioctl

	- When the device encounters an error, the eventfd is signalled
          and the qemu eventfd handler gets invoked.

	- In the handler decide what action to take. Current action taken
          is to stop the guest.
Signed-off-by: NVijay Mohan Pandarathil <vijaymohan.pandarathil@hp.com>
Signed-off-by: NAlex Williamson <alex.williamson@redhat.com>
      7b4b0e9e
    • A
      vfio-pci: VGA quirk update · 39360f0b
      由 Alex Williamson 提交于 
      Turns out all the suspicions for AMD devices were correct, everywhere
we read a BAR address that the address matches the config space offset,
there's full access to PCI config space.  Attempt to generalize some
helpers to allow quirks to easily be added for mirrors and windows.
Also fill in complete config space for AMD.
Signed-off-by: NAlex Williamson <alex.williamson@redhat.com>
      39360f0b
    • A
      Merge remote-tracking branch 'quintela/migration.next' into staging · 6453a3a6
      由 Anthony Liguori 提交于 
      # By Chegu Vinod
# Via Juan Quintela
* quintela/migration.next:
  Force auto-convegence of live migration
  Add 'auto-converge' migration capability
  Introduce async_run_on_cpu()

Message-id: 1373664508-5404-1-git-send-email-quintela@redhat.com
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
      6453a3a6
    • A
      Merge remote-tracking branch 'cohuck/virtio-ccw-upstr' into staging · 2562becf
      由 Anthony Liguori 提交于 
      # By Dominik Dingel
# Via Cornelia Huck
* cohuck/virtio-ccw-upstr:
  virtio-ccw: Enable x-data-plane for virtio-ccw-blk

Message-id: 1373903207-27085-1-git-send-email-cornelia.huck@de.ibm.com
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
      2562becf
    • A
      Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20130715-1' into staging · ab4e1589
      由 Anthony Liguori 提交于 
      target-arm queue

# gpg: Signature made Mon 15 Jul 2013 11:15:13 AM CDT using RSA key ID 14360CDE
# gpg: Can't check signature: public key not found

# By Mans Rullgard (3) and others
# Via Peter Maydell
* pmaydell/tags/pull-target-arm-20130715-1:
  target-arm: Avoid g_hash_table_get_keys()
  target-arm: avoid undefined behaviour when writing TTBCR
  target-arm/helper.c: Allow const opaques in arm CP
  target-arm/helper.c: Implement MIDR aliases
  target-arm/helper.c: OMAP/StrongARM cp15 crn=0 cleanup
  target-arm: explicitly decode SEVL instruction
  target-arm: implement LDA/STL instructions
  target-arm: add feature flag for ARMv8

Message-id: 1373905022-27735-1-git-send-email-peter.maydell@linaro.org
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
      ab4e1589
    • A
      Merge remote-tracking branch 'pmaydell/tags/pull-arm-devs-20130715' into staging · 1750d019
      由 Anthony Liguori 提交于 
      arm-devs queue

# gpg: Signature made Mon 15 Jul 2013 10:53:44 AM CDT using RSA key ID 14360CDE
# gpg: Can't check signature: public key not found

# By Peter Maydell (4) and others
# Via Peter Maydell
* pmaydell/tags/pull-arm-devs-20130715:
  ARM/highbank: add support for Calxeda ECX-2000 / Midway
  ARM/highbank: prepare for adding similar machines
  hw/arm/vexpress: Add alias for flash at address 0 on A15 board
  hw/dma/omap_dma: Fix bugs with DMA requests above 32
  sd/pl181.c: Avoid undefined shift behaviour in RWORD macro
  hw/cpu/a15mpcore: Correct default value for num-irq
  char/cadence_uart: Fix reset for unattached instances

Message-id: 1373904095-27592-1-git-send-email-peter.maydell@linaro.org
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
      1750d019
    • A
      Merge remote-tracking branch 'rth/axp-next' into staging · a34001fa
      由 Anthony Liguori 提交于 
      # By Richard Henderson
# Via Richard Henderson
* rth/axp-next:
  hw/alpha: Use SRM epoch
  hw/alpha: Drop latch_tmp hack
  exec: Support 64-bit operations in address_space_rw
  hw/alpha: Don't machine check on missing pci i/o
  hw/alpha: Don't use get_system_io

Message-id: 1373840171-25556-1-git-send-email-rth@twiddle.net
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
      a34001fa
    • A
      Merge remote-tracking branch 'kwolf/for-anthony' into staging · 5699a02e
      由 Anthony Liguori 提交于 
      # By Kevin Wolf (6) and Stefan Hajnoczi (2)
# Via Kevin Wolf
* kwolf/for-anthony:
  ahci: Fix FLUSH command
  migration: Fail migration on bdrv_flush_all() error
  cpus: Add return value for vm_stop()
  block: Add return value for bdrv_flush_all()
  qemu-iotests: Update 051 reference output
  block: Don't parse protocol from file.filename
  block: add drive_backup HMP command
  blockdev: add sync mode to drive-backup QMP command

Message-id: 1373887000-4488-1-git-send-email-kwolf@redhat.com
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
      5699a02e
    • M
      pc: don't access fw cfg if NULL · d26d9e14
      由 Michael S. Tsirkin 提交于 
      commit f8c457b8
     "pc: pass PCI hole ranges to Guests"
broke Xen as it has no fw_cfg.
Check for this configuration and boil out.
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
Tested-by: NStefano Stabellini <stefano.stabellini@eu.citrix.com>
      d26d9e14
    • M
      virtio-net: add feature bit for any header s/g · 488f069b
      由 Michael S. Tsirkin 提交于 
      Old qemu versions required that 1st s/g entry is the header.

Since QEMU 1.5, patchset titled "virtio-net: iovec handling cleanup"
removed this limitation but a feature bit is needed so guests know it's
safe to lay out header differently.

This patch applies on top and adds such a feature bit to QEMU.
It is set by default for virtio-net.
virtio net header inline with the data is beneficial
for latency and small packet bandwidth - guest driver
code utilizing this feature has been acked but missed 3.11
by a narrow margin, it's pending for 3.12.

This feature bit is cleared by default when compatibility with old
machine types is requested.

Other performance-sensitive devices (blk and scsi)
don't yet support arbitrary s/g layouts, so
we only set this bit for virtio-net for now.
There are plans to allow arbitrary layouts there, but
no code has been posted yet.

Cc: Rusty Russell <rusty@rustcorp.com.au>
Reviewed-by: NLaszlo Ersek <lersek@redhat.com>
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
      488f069b
    • A
      net: add support of mac-programming over macvtap in QEMU side · b1be4280
      由 Amos Kong 提交于 
      Currently macvtap based macvlan device is working in promiscuous
mode, we want to implement mac-programming over macvtap through
Libvirt for better performance.

Design:
 QEMU notifies Libvirt when rx-filter config is changed in guest,
 then Libvirt query the rx-filter information by a monitor command,
 and sync the change to macvtap device. Related rx-filter config
 of the nic contains main mac, rx-mode items and vlan table.

This patch adds a QMP event to notify management of rx-filter change,
and adds a monitor command for management to query rx-filter
information.

Test:
 If we repeatedly add/remove vlan, and change macaddr of vlan
 interfaces in guest by a loop script.

Result:
 The events will flood the QMP client(management), management takes
 too much resource to process the events.

 Event_throttle API (set rate to 1 ms) can avoid the events to flood
 QMP client, but it could cause an unexpected delay (~1ms), guests
 guests normally expect rx-filter updates immediately.

 So we use a flag for each nic to avoid events flooding, the event
 is emitted once until the query command is executed. The flag
 implementation could not introduce unexpected delay.

There maybe exist an uncontrollable delay if we let Libvirt do the
real change, guests normally expect rx-filter updates immediately.
But it's another separate issue, we can investigate it when the
work in Libvirt side is done.

Michael S. Tsirkin: tweaked to enable events on start
Michael S. Tsirkin: fixed not to crash when no id
Michael S. Tsirkin: fold in patch:
   "additional fixes for mac-programming feature"
Amos Kong: always notify QMP client if mactable is changed
Amos Kong: return NULL list if no net client supports rx-filter query
Reviewed-by: NEric Blake <eblake@redhat.com>
Reviewed-by: NMarkus Armbruster <armbru@redhat.com>
Signed-off-by: NAmos Kong <akong@redhat.com>
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
      b1be4280
    • P
      target-arm: Avoid g_hash_table_get_keys() · 82a3a118
      由 Peter Maydell 提交于 
      g_hash_table_get_keys() was only introduced in glib 2.14, and we're
still targeting a minimum version of 2.12.  Rewrite the offending
code (introduced in commit 721fae12) to use g_hash_table_foreach()
to build the list of keys.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Tested-by: NLaurent Desnogues <laurent.desnogues@gmail.com>
Tested-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1372678819-8633-1-git-send-email-peter.maydell@linaro.org
      82a3a118
    • P
      target-arm: avoid undefined behaviour when writing TTBCR · 2ebcebe2
      由 Peter Maydell 提交于 
      LPAE CPUs have more potentially valid bits in the TTBCR, and so the
simple masking out of invalid bits is no longer sufficient to obtain
the base address width field of the register, which is what we use to
precalculate c2_mask and c2_base_mask.  Explicitly extract the
relevant register field rather than simply shifting by the register
value.

This bug would have had no ill effects in practice, since if the
EAE bit (TTBCR bit 31) is set then we don't use the precalculated
masks, and if EAE is zero then bits 30..3 are all UNK/SBZP, so
well-behaved guests won't set them. However the shift is undefined
behaviour, so we should avoid it.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1372347527-4428-1-git-send-email-peter.maydell@linaro.org
      2ebcebe2
    • P
      target-arm/helper.c: Allow const opaques in arm CP · 204a9c43
      由 Peter Crosthwaite 提交于 
      Allow for defining const opaque data in ARM CP register definitions by
setting .opaque = foo. If non null opaque is passed into
define_one_arm_cp_reg_with_opaque then that opaque will take
precedence, otherwise if null opaque is passed, the original opaque
data will be used.
Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: cf0a3ac3438d97464240db9f5f4ef1585cbc1d77.1373429432.git.peter.crosthwaite@xilinx.com
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      204a9c43
    • P
      target-arm/helper.c: Implement MIDR aliases · 97ce8d61
      由 Peter Crosthwaite 提交于 
      Unimplemented registers in the cp15, CRn=0, opc1=0, CRm=0 space default
to aliasing the MIDR register. Set all registers in the space to access
MIDR by default.
Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 6127846712b7ad2727354a4f5e1d809451f1e859.1373429432.git.peter.crosthwaite@xilinx.com
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      97ce8d61
    • P
      target-arm/helper.c: OMAP/StrongARM cp15 crn=0 cleanup · a703eda1
      由 Peter Crosthwaite 提交于 
      The if block detecting OMAP/StrongARM modifies the id_cp_reginfo
.access fields in place. So there is no need to replicate the call
to define_arm_cp_reg(). Dropped, and let the OMAP case fall through
to the normal behaviour after the in-place modification.
Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 72aae9b8ebbc9a76d2b06faf8666ef8a4b34b92a.1373429432.git.peter.crosthwaite@xilinx.com
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      a703eda1
    • M
      target-arm: explicitly decode SEVL instruction · 12b10571
      由 Mans Rullgard 提交于 
      The ARMv8 SEVL instruction is in the architectural hint space already
emulated as nop.  This makes the decoding of SEVL explicit for clarity.
Signed-off-by: NMans Rullgard <mans@mansr.com>
Message-id: 1370606786-5650-3-git-send-email-mans@mansr.com
[PMM: added 'SEVL' to the TODO comment]
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      12b10571
    • M
      target-arm: implement LDA/STL instructions · 2359bf80
      由 Mans Rullgard 提交于 
      This adds support for the ARMv8 load acquire/store release instructions.
Since qemu does nothing special for memory barriers, these can be
emulated like their non-acquire/release counterparts.
Signed-off-by: NMans Rullgard <mans@mansr.com>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      2359bf80
  9. 15 7月, 2013 8 次提交