- 03 6月, 2015 22 次提交
-
-
由 Sai Pavan Boddu 提交于
This patch corrects the Rx buffer size field mask to mask bits 23 to 16 to match Xilinx UG585 documentation. Signed-off-by: NSai Pavan Boddu <saipava@xilinx.com> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
-
由 Shannon Zhao 提交于
Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
-
由 Shannon Zhao 提交于
Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
-
由 Shannon Zhao 提交于
Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
-
由 Shannon Zhao 提交于
Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
-
由 Shannon Zhao 提交于
Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
-
由 Shannon Zhao 提交于
Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
-
由 Shannon Zhao 提交于
Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
-
由 Shannon Zhao 提交于
Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
-
由 Shannon Zhao 提交于
Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
-
由 Shannon Zhao 提交于
Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
-
由 Shannon Zhao 提交于
Since ich9_lpc_pm_init only requests one irq, so let it just call qemu_allocate_irq. Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
-
由 Shannon Zhao 提交于
Since pc_allocate_cpu_irq only requests one irq, so let it just call qemu_allocate_irq. Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
-
由 Shannon Zhao 提交于
Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
-
由 Shannon Zhao 提交于
Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
-
由 Shannon Zhao 提交于
Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
-
由 Shannon Zhao 提交于
valgrind complains about: ==7055== 58 bytes in 1 blocks are definitely lost in loss record 1,471 of 2,192 ==7055== at 0x4C2845D: malloc (in /usr/lib64/valgrind/vgpreload_memcheck-amd64-linux.so) ==7055== by 0x24410F: malloc_and_trace (vl.c:2556) ==7055== by 0x64C770E: g_malloc (in /usr/lib64/libglib-2.0.so.0.3600.3) ==7055== by 0x64DEFD7: g_strndup (in /usr/lib64/libglib-2.0.so.0.3600.3) ==7055== by 0x650181A: g_vasprintf (in /usr/lib64/libglib-2.0.so.0.3600.3) ==7055== by 0x64DF0CC: g_strdup_vprintf (in /usr/lib64/libglib-2.0.so.0.3600.3) ==7055== by 0x64DF188: g_strdup_printf (in /usr/lib64/libglib-2.0.so.0.3600.3) ==7055== by 0x242F81: qemu_find_file (vl.c:2121) ==7055== by 0x217A32: clipper_init (dp264.c:105) ==7055== by 0x2484DA: main (vl.c:4249) Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
-
由 Shannon Zhao 提交于
valgrind complains about: ==16447== 48 bytes in 2 blocks are definitely lost in loss record 2,033 of 3,310 ==16447== at 0x4C2845D: malloc (in /usr/lib64/valgrind/vgpreload_memcheck-amd64-linux.so) ==16447== by 0x2E4FD7: malloc_and_trace (vl.c:2546) ==16447== by 0x64C770E: g_malloc (in /usr/lib64/libglib-2.0.so.0.3600.3) ==16447== by 0x53EC3F: qint_from_int (qint.c:33) ==16447== by 0x53B426: qmp_output_type_int (qmp-output-visitor.c:162) ==16447== by 0x539257: visit_type_uint32 (qapi-visit-core.c:147) ==16447== by 0x471D07: property_get_uint32_ptr (object.c:1651) ==16447== by 0x47000C: object_property_get (object.c:822) ==16447== by 0x472428: object_property_get_qobject (qom-qobject.c:37) ==16447== by 0x25701A: build_append_pci_bus_devices (acpi-build.c:520) ==16447== by 0x25902E: build_ssdt (acpi-build.c:1004) ==16447== by 0x25A0A8: acpi_build (acpi-build.c:1420) Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Reviewed-by: NIgor Mammedov <imammedo@redhat.com> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
-
由 Shannon Zhao 提交于
valgrind complains about: ==16447== 16 bytes in 2 blocks are definitely lost in loss record 1,304 of 3,310 ==16447== at 0x4C2845D: malloc (in /usr/lib64/valgrind/vgpreload_memcheck-amd64-linux.so) ==16447== by 0x2E4FD7: malloc_and_trace (vl.c:2546) ==16447== by 0x64C770E: g_malloc (in /usr/lib64/libglib-2.0.so.0.3600.3) ==16447== by 0x36FB47: qemu_extend_irqs (irq.c:55) ==16447== by 0x36FBD3: qemu_allocate_irqs (irq.c:64) ==16447== by 0x3B4B44: bmdma_init (pci.c:464) ==16447== by 0x3B547B: pci_piix_init_ports (piix.c:144) ==16447== by 0x3B55D2: pci_piix_ide_realize (piix.c:164) ==16447== by 0x3EAEC6: pci_qdev_realize (pci.c:1790) ==16447== by 0x36C685: device_set_realized (qdev.c:1058) ==16447== by 0x47179E: property_set_bool (object.c:1514) ==16447== by 0x470098: object_property_set (object.c:837) Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Reviewed-by: NMarcel Apfelbaum <marcel@redhat.com> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
-
由 Shannon Zhao 提交于
valgrind complains about: ==16447== 8 bytes in 1 blocks are definitely lost in loss record 552 of 3,310 ==16447== at 0x4C2845D: malloc (in /usr/lib64/valgrind/vgpreload_memcheck-amd64-linux.so) ==16447== by 0x2E4FD7: malloc_and_trace (vl.c:2546) ==16447== by 0x64C770E: g_malloc (in /usr/lib64/libglib-2.0.so.0.3600.3) ==16447== by 0x36FB47: qemu_extend_irqs (irq.c:55) ==16447== by 0x36FBD3: qemu_allocate_irqs (irq.c:64) ==16447== by 0x24E622: pc_init1 (pc_piix.c:287) ==16447== by 0x24E76A: pc_init_pci (pc_piix.c:310) ==16447== by 0x2E9360: main (vl.c:4226) ==16447== 128 bytes in 1 blocks are definitely lost in loss record 2,569 of 3,310 ==16447== at 0x4C2845D: malloc (in /usr/lib64/valgrind/vgpreload_memcheck-amd64-linux.so) ==16447== by 0x2E4FD7: malloc_and_trace (vl.c:2546) ==16447== by 0x64C770E: g_malloc (in /usr/lib64/libglib-2.0.so.0.3600.3) ==16447== by 0x36FB47: qemu_extend_irqs (irq.c:55) ==16447== by 0x36FBD3: qemu_allocate_irqs (irq.c:64) ==16447== by 0x25BEB2: kvm_i8259_init (i8259.c:133) ==16447== by 0x24E1F1: pc_init1 (pc_piix.c:219) ==16447== by 0x24E76A: pc_init_pci (pc_piix.c:310) ==16447== by 0x2E9360: main (vl.c:4226) Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Reviewed-by: NMarcel Apfelbaum <marcel@redhat.com> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
-
由 Zhu Guihua 提交于
Use C casts to avoid accessing ICCDevice's qdev field directly. Signed-off-by: NZhu Guihua <zhugh.fnst@cn.fujitsu.com> Reviewed-by: NIgor Mammedov <imammedo@redhat.com> Reviewed-by: NAndreas Färber <afaerber@suse.de> Acked-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
-
由 Andreas Färber 提交于
Setting the parent bus of a device increases its ref count, which we ultimately want to level out. However it is only safe to do so after the last reference to the device in local code, as qom-set or similar operations might decrease the ref count. Therefore move the object_unref() from pc_new_cpu() into its callers. The APIC operations on the last CPU in pc_cpus_init() are still potentially insecure, but that is beyond the scope of this code movement. Signed-off-by: NAndreas Färber <afaerber@suse.de> Acked-by: NMichael S. Tsirkin <mst@redhat.com> Reviewed-by: NEduardo Habkost <ehabkost@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
-
- 02 6月, 2015 18 次提交
-
-
由 Eric Auger 提交于
Re-indent in a15memmap after VIRT_PLATFORM_BUS introduction Signed-off-by: NEric Auger <eric.auger@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Reviewed-by: NShannon Zhao <shannon.zhao@linaro.org> Message-id: 1433244554-12898-5-git-send-email-eric.auger@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Eric Auger 提交于
Allows sysbus devices to be instantiated from command line by using -device option. Machvirt creates a platform bus at init. The dynamic sysbus devices are attached to this platform bus device. The platform bus device registers a machine init done notifier whose role will be to bind the dynamic sysbus devices. Indeed dynamic sysbus devices are created after machine init. machvirt also registers a notifier that will build the device tree nodes for the platform bus and its children dynamic sysbus devices. Signed-off-by: NEric Auger <eric.auger@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 1433244554-12898-4-git-send-email-eric.auger@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Eric Auger 提交于
Device tree nodes for the platform bus and its children dynamic sysbus devices are added in a machine init done notifier. To load the dtb once, after those latter nodes are built and before ROM freeze, the actual arm_load_kernel existing code is moved into a notifier notify function, arm_load_kernel_notify. arm_load_kernel now only registers the corresponding notifier. Machine files that do not support platform bus stay unchanged. Machine files willing to support dynamic sysbus devices must call arm_load_kernel before sysbus-fdt arm_register_platform_bus_fdt_creator to make sure dynamic sysbus device nodes are integrated in the dtb. Signed-off-by: NEric Auger <eric.auger@linaro.org> Reviewed-by: NShannon Zhao <zhaoshenglong@huawei.com> Reviewed-by: NAlexander Graf <agraf@suse.de> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 1433244554-12898-3-git-send-email-eric.auger@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Jan Beulich 提交于
... by default. Add a per-device "permissive" mode similar to pciback's to allow restoring previous behavior (and hence break security again, i.e. should be used only for trusted guests). This is part of XSA-131. Signed-off-by: NJan Beulich <jbeulich@suse.com> Acked-by: NStefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com>)
-
由 Jan Beulich 提交于
Since the next patch will turn all not explicitly described fields read-only by default, those fields that have guest writable bits need to be given explicit descriptors. This is a preparatory patch for XSA-131. Signed-off-by: NJan Beulich <jbeulich@suse.com>
-
由 Jan Beulich 提交于
The adjustments are solely to make the subsequent patches work right (and hence make the patch set consistent), namely if permissive mode (introduced by the last patch) gets used (as both reserved registers and reserved fields must be similarly protected from guest access in default mode, but the guest should be allowed access to them in permissive mode). This is a preparatory patch for XSA-131. Signed-off-by: NJan Beulich <jbeulich@suse.com>
-
由 Jan Beulich 提交于
xen_pt_emu_reg_pcie[]'s PCI_EXP_DEVCAP needs to cover all bits as read- only to avoid unintended write-back (just a precaution, the field ought to be read-only in hardware). This is a preparatory patch for XSA-131. Signed-off-by: NJan Beulich <jbeulich@suse.com> Reviewed-by: NStefano Stabellini <stefano.stabellini@eu.citrix.com>
-
由 Jan Beulich 提交于
This is just to avoid having to adjust that calculation later in multiple places. Note that including ->ro_mask in get_throughable_mask()'s calculation is only an apparent (i.e. benign) behavioral change: For r/o fields it doesn't matter > whether they get passed through - either the same flag is also set in emu_mask (then there's no change at all) or the field is r/o in hardware (and hence a write won't change it anyway). This is a preparatory patch for XSA-131. Signed-off-by: NJan Beulich <jbeulich@suse.com> Acked-by: NStefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: NAnthony PERARD <anthony.perard@citrix.com>
-
由 Jan Beulich 提交于
xen_pt_pmcsr_reg_write() needs an adjustment to deal with the RW1C nature of the not passed through bit 15 (PCI_PM_CTRL_PME_STATUS). This is a preparatory patch for XSA-131. Signed-off-by: NJan Beulich <jbeulich@suse.com> Reviewed-by: NStefano Stabellini <stefano.stabellini@eu.citrix.com>
-
由 Jan Beulich 提交于
There's no point in xen_pt_pmcsr_reg_{read,write}() each ORing PCI_PM_CTRL_STATE_MASK and PCI_PM_CTRL_NO_SOFT_RESET into a local emu_mask variable - we can have the same effect by setting the field descriptor's emu_mask member suitably right away. Note that xen_pt_pmcsr_reg_write() is being retained in order to allow later patches to be less intrusive. This is a preparatory patch for XSA-131. Signed-off-by: NJan Beulich <jbeulich@suse.com> Acked-by: NStefano Stabellini <stefano.stabellini@eu.citrix.com> Acked-by: NIan Campbell <ian.campbell@citrix.com>
-
由 Jan Beulich 提交于
Without this the actual XSA-131 fix would cause the enable bit to not get set anymore (due to the write back getting suppressed there based on the OR of emu_mask, ro_mask, and res_mask). Note that the fiddling with the enable bit shouldn't really be done by qemu, but making this work right (via libxc and the hypervisor) will require more extensive changes, which can be postponed until after the security issue got addressed. This is a preparatory patch for XSA-131. Signed-off-by: NJan Beulich <jbeulich@suse.com> Acked-by: NStefano Stabellini <stefano.stabellini@eu.citrix.com>
-
由 Jan Beulich 提交于
Limit error messages resulting from bad guest behavior to avoid allowing the guest to cause the control domain's disk to fill. The first message in pci_msix_write() can simply be deleted, as this is indeed bad guest behavior, but such out of bounds writes don't really need to be logged. The second one is more problematic, as there guest behavior may only appear to be wrong: For one, the old logic didn't take the mask-all bit into account. And then this shouldn't depend on host device state (i.e. the host may have masked the entry without the guest having done so). Plus these writes shouldn't be dropped even when an entry is unmasked. Instead, if they can't be made take effect right away, they should take effect on the next unmasking or enabling operation - the specification explicitly describes such caching behavior. Until we can validly drop the message (implementing such caching/latching behavior), issue the message just once per MSI-X table entry. Note that the log message in pci_msix_read() similar to the one being removed here is not an issue: "addr" being of unsigned type, and the maximum size of the MSI-X table being 32k, entry_nr simply can't be negative and hence the conditonal guarding issuing of the message will never be true. This is XSA-130. Signed-off-by: NJan Beulich <jbeulich@suse.com> Reviewed-by: NStefano Stabellini <stefano.stabellini@eu.citrix.com>
-
由 Jan Beulich 提交于
It's being used by the hypervisor. For now simply mimic a device not capable of masking, and fully emulate any accesses a guest may issue nevertheless as simple reads/writes without side effects. This is XSA-129. Signed-off-by: NJan Beulich <jbeulich@suse.com> Reviewed-by: NStefano Stabellini <stefano.stabellini@eu.citrix.com>
-
由 Jan Beulich 提交于
The old logic didn't work as intended when an access spanned multiple fields (for example a 32-bit access to the location of the MSI Message Data field with the high 16 bits not being covered by any known field). Remove it and derive which fields not to write to from the accessed fields' emulation masks: When they're all ones, there's no point in doing any host write. This fixes a secondary issue at once: We obviously shouldn't make any host write attempt when already the host read failed. This is XSA-128. Signed-off-by: NJan Beulich <jbeulich@suse.com> Reviewed-by: NStefano Stabellini <stefano.stabellini@eu.citrix.com>
-
由 Eric Auger 提交于
This new C module will be used by ARM machine files to generate platform bus node and their dynamic sysbus device tree nodes. Dynamic sysbus device node addition is done in a machine init done notifier. arm_register_platform_bus_fdt_creator does the registration of this latter and is supposed to be called by ARM machine files that support platform bus and their dynamic sysbus. Addition of dynamic sysbus nodes is done only if the user did not provide any dtb. Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NEric Auger <eric.auger@linaro.org> Reviewed-by: NShannon Zhao <zhaoshenglong@huawei.com> Reviewed-by: NAlexander Graf <agraf@suse.de> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 1433244554-12898-2-git-send-email-eric.auger@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Eric Auger 提交于
After introduction of kvm_arch_msi_data_to_gsi, kvm_gsi_direct_mapping now can be set on ARM. Also kvm_msi_via_irqfd_allowed can be set, depending on kernel irqfd support, hence enabling VIRTIO-PCI with vhost back-end. Signed-off-by: NEric Auger <eric.auger@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Victor CLEMENT 提交于
The masked interrupt status register should be the state of the interrupt after masking. There should be a logical AND instead of a logical OR between the interrupt status and the interrupt mask. Signed-off-by: NVictor CLEMENT <victor.clement@openwide.fr> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1433154824-6927-1-git-send-email-victor.clement@openwide.fr Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Christoffer Dall 提交于
Add a GICv2m device to the virt board to enable MSIs on the generic PCI host controller. We allocate 64 SPIs in the IRQ space for now (this can be increased/decreased later) and map the GICv2m right after the GIC in the memory map. Reviewed-by: NEric Auger <eric.auger@linaro.org> Signed-off-by: NChristoffer Dall <christoffer.dall@linaro.org> Message-id: 1432897270-7780-5-git-send-email-christoffer.dall@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-