1. 10 9月, 2010 2 次提交
    • S
      trace: Add simple built-in tracing backend · 26f7227b
      Stefan Hajnoczi 提交于
      This patch adds a simple tracer which produces binary trace files.  To
      try out the simple backend:
      
      $ ./configure --trace-backend=simple
      $ make
      
      After running QEMU you can pretty-print the trace:
      
      $ ./simpletrace.py trace-events trace.log
      
      The output of simpletrace.py looks like this:
      
        qemu_realloc 0.699 ptr=0x24363f0 size=0x3 newptr=0x24363f0
        qemu_free 0.768 ptr=0x24363f0
        ^           ^---- timestamp delta (us)
        |____ trace event name
      Signed-off-by: NStefan Hajnoczi <stefanha@linux.vnet.ibm.com>
      
      trace: Make trace record fields 64-bit
      
      Explicitly use 64-bit fields in trace records so that timestamps and
      magic numbers work for 32-bit host builds.
      
      Includes fixes from Prerna Saxena <prerna@linux.vnet.ibm.com>.
      Signed-off-by: NPrerna Saxena <prerna@linux.vnet.ibm.com>
      Signed-off-by: NStefan Hajnoczi <stefanha@linux.vnet.ibm.com>
      26f7227b
    • S
      trace: Add trace-events file for declaring trace events · 94a420b1
      Stefan Hajnoczi 提交于
      This patch introduces the trace-events file where trace events can be
      declared like so:
      
      qemu_malloc(size_t size) "size %zu"
      qemu_free(void *ptr) "ptr %p"
      
      These trace event declarations are processed by a new tool called
      tracetool to generate code for the trace events.  Trace event
      declarations are independent of the backend tracing system (LTTng User
      Space Tracing, ftrace markers, DTrace).
      
      The default "nop" backend generates empty trace event functions.
      Therefore trace events are disabled by default.
      
      The trace-events file serves two purposes:
      
      1. Adding trace events is easy.  It is not necessary to understand the
         details of a backend tracing system.  The trace-events file is a
         single location where trace events can be declared without code
         duplication.
      
      2. QEMU is not tightly coupled to one particular backend tracing system.
         In order to support tracing across QEMU host platforms and to
         anticipate new backend tracing systems that are currently maturing,
         it is important to be flexible and not tied to one system.
      
      This commit includes fixes from Prerna Saxena
      <prerna@linux.vnet.ibm.com> and Blue Swirl <blauwirbel@gmail.com>.
      Signed-off-by: NStefan Hajnoczi <stefanha@linux.vnet.ibm.com>
      94a420b1
  2. 27 8月, 2010 1 次提交
  3. 27 7月, 2010 5 次提交
  4. 30 6月, 2010 1 次提交
  5. 23 6月, 2010 1 次提交
  6. 13 6月, 2010 1 次提交
  7. 12 6月, 2010 2 次提交
  8. 10 6月, 2010 16 次提交
  9. 09 6月, 2010 1 次提交
  10. 02 6月, 2010 1 次提交
    • J
      QMP: Introduce commands documentation · b40292e7
      Jan Kiszka 提交于
      One of the most important missing feature in QMP today is its
      supported commands documentation.
      
      The plan is to make it part of self-description support, however
      self-description is a big task we have been postponing for a
      long time now and still don't know when it's going to be done.
      
      In order not to compromise QMP adoption and make users' life easier,
      this commit adds a simple text documentation which fully describes
      all QMP supported commands.
      
      This is not ideal for a number of reasons (harder to maintain,
      text-only, etc) but does improve the current situation. To avoid at
      least divering from the user monitor help and texi snippets, QMP bits
      are also maintained inside qemu-monitor.hx, and hxtool is extended to
      generate a single text file from them.
      Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com>
      Signed-off-by: NLuiz Capitulino <lcapitulino@redhat.com>
      Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
      b40292e7
  11. 19 5月, 2010 1 次提交
    • S
      Fix cross compilation · fec0e3e8
      Stefan Weil 提交于
      This patch enhances the algorithm which finds the correct settings for SDL.
      For cross compilations (when cross_prefix is set), it looks for sdl-config
      with cross prefix. Here is the complete search order:
      
      $(cross_prefix}pkg-config              (old, only used for cross compilation)
      ${cross_prefix}sdl_config              (new, only used for cross compilation)
      pkg-config                             (old, needs PATH)
      sdl-config                             (old, needs PATH)
      
      Cross SDL packages (or the user) now can simply set a link (for example
      /usr/bin/i586-mingw32msvc-sdl-config -> /usr/i586-mingw32msvc/bin/sdl-config)
      which allows cross compilations without PATH modifications.
      
      Without the patch, configure and make (which calls configure) typically
      need a non-standard PATH. Failing to set this special PATH results in
      broken builds.
      Signed-off-by: NStefan Weil <weil@mail.berlios.de>
      Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      fec0e3e8
  12. 05 5月, 2010 1 次提交
  13. 04 5月, 2010 1 次提交
  14. 27 4月, 2010 1 次提交
  15. 25 4月, 2010 1 次提交
  16. 14 4月, 2010 1 次提交
  17. 08 4月, 2010 1 次提交
    • R
      tcg-hppa: Finish the port. · fd76e73a
      Richard Henderson 提交于
      Delete inline functions from tcg-target.h that don't need to be there,
      move the others to tcg-target.c.  Add 'Z', 'I', 'J' constraints for
      0, signed 11-bit, and signed 5-bit respectively.  Add GUEST_BASE support
      similar to ppc64, with the value stored in a register.  Add missing
      registers to reg_alloc_order.  Add support for 12-bit branch relocations.
      Add functions for synthetic operations: addi, mtctl, dep, shd, vshd, ori,
      andi, shifts, rotates, multiply, branches, setcond.  Split out TLB reads
      from qemu_ld and qemu_st; fix argument loading for tlb external calls.
      Generate the prologue.
      Signed-off-by: NRichard Henderson <rth@twiddle.net>
      Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      fd76e73a
  18. 05 4月, 2010 1 次提交
    • P
      Split TLB addend and target_phys_addr_t · 355b1943
      Paul Brook 提交于
      Historically the qemu tlb "addend" field was used for both RAM and IO accesses,
      so needed to be able to hold both host addresses (unsigned long) and guest
      physical addresses (target_phys_addr_t).  However since the introduction of
      the iotlb field it has only been used for RAM accesses.
      
      This means we can change the type of addend to unsigned long, and remove
      associated hacks in the big-endian TCG backends.
      
      We can also remove the host dependence from target_phys_addr_t.
      Signed-off-by: NPaul Brook <paul@codesourcery.com>
      355b1943
  19. 02 4月, 2010 1 次提交
    • A
      tcg: initial ia64 support · 477ba620
      Aurelien Jarno 提交于
      A few words about design choices:
      * On IA64, instructions should be grouped by bundle, and dependencies
        between instructions declared. A first version of this code tried to
        schedule instructions automatically, but was very complex and too
        invasive for the current common TCG code (ops not ending at
        instruction boundaries, code retranslation breaking already generated
        code, etc.)  It was also not very efficient, as dependencies between
        TCG ops is not available.
        Instead the option taken by the current implementation does not try
        to fill the bundle by scheduling instructions, but by providing ops
        not available as an ia64 instruction, and by offering 22-bit constant
        loading for most of the instructions. With both options the bundle are
        filled at approximately the same level.
      
      * Up to 128 registers can be affected to a function on IA64, but TCG
        limits this number to 64, which is actually more than enough. The
        register affectation is the following:
        - r0: used to map a constant argument with value 0
        - r1: global pointer
        - r2, r3: internal use
        - r4 to r6: not used to avoid saving them
        - r7: env structure
        - r8 to r11: free for TCG (call clobbered)
        - r12: stack pointer
        - r13: thread pointer
        - r14 to r31: free for TCG (call clobbered)
        - r32: reserved (return address)
        - r33: reserved (PFS)
        - r33 to r63: free for TCG
      
      * The IA64 architecture has only 64-bit registers and no 32-bit
        instructions (the only exception being cmp4). Therefore 64-bit
        registers and instructions are used for 32-bit ops. The adopted
        strategy is the same as the ABI, that is the higher 32 bits are
        undefined. Most ops (and, or, add, shl, etc.) can directly use
        the 64-bit registers, while some others have to sign-extend (sar,
        div, etc.) or zero-extend (shr, divu, etc.) the register first.
      Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      477ba620