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  1. 12 7月, 2013 2 次提交
  3. 10 7月, 2013 2 次提交
  5. 01 7月, 2013 5 次提交
  7. 28 6月, 2013 2 次提交
  9. 06 5月, 2013 1 次提交
  11. 27 4月, 2013 7 次提交
  13. 22 3月, 2013 4 次提交
    • D
      target-ppc: Use QOM method dispatch for MMU fault handling · b632a148
      由 David Gibson 提交于 
      After previous cleanups, the many scattered checks of env->mmu_model in
the ppc MMU implementation have, at least for "classic" hash MMUs been
reduced (almost) to a single switch at the top of
cpu_ppc_handle_mmu_fault().

An explicit switch is still a pretty ugly way of handling this though.  Now
that Andreas Färber's CPU QOM cleanups for ppc have gone in, it's quite
straightforward to instead make the handle_mmu_fault function a QOM method
on the CPU object.

This patch implements such a scheme, initializing the method pointer at
the same time as the mmu_model variable.  We need to keep the latter around
for now, because of the MMU types (BookE, 4xx, et al) which haven't been
converted to the new scheme yet, and also for a few other uses.  It would
be good to clean those up eventually.
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
Signed-off-by: NAlexander Graf <agraf@suse.de>
      b632a148
    • D
      mmu-hash64: Implement Virtual Page Class Key Protection · f80872e2
      由 David Gibson 提交于 
      Version 2.06 of the Power architecture describes an additional page
protection mechanism.  Each virtual page has a "class" (0-31) recorded in
the PTE.  The AMR register contains bits which can prohibit reads and/or
writes on a class by class basis.  Interestingly, the AMR is userspace
readable and writable, however user mode writes are masked by the contents
of the UAMOR which is privileged.

This patch implements this protection mechanism, along with the AMR and
UAMOR SPRs.  The architecture also specifies a hypervisor-privileged AMOR
register which masks user and supervisor writes to the AMR and UAMOR.  We
leave this out for now, since we don't at present model hypervisor mode
correctly in any case.
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
[agraf: fix 32-bit hosts]
Signed-off-by: NAlexander Graf <agraf@suse.de>
      f80872e2
    • D
      target-ppc: Remove vestigial PowerPC 620 support · 9baea4a3
      由 David Gibson 提交于 
      The PowerPC 620 was the very first 64-bit PowerPC implementation, but
hardly anyone ever actually used the chips.  qemu notionally supports the
620, but since we don't actually have code to implement the segment table,
the support is broken (quite likely in other ways too).

This patch, therefore, removes all remaining pieces of 620 support, to
stop it cluttering up the platforms we actually care about.  This includes
removing support for the ASR register, used only on segment table based
machines.
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
Signed-off-by: NAlexander Graf <agraf@suse.de>
      9baea4a3
    • F
      PPC/GDB: handle read and write of fpscr · d6478bc7
      由 Fabien Chouteau 提交于 
      Although the support of this register may be uncomplete, there are no
reason to prevent the debugger from reading or writing it.
Signed-off-by: NFabien Chouteau <chouteau@adacore.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>
      d6478bc7
  15. 12 3月, 2013 1 次提交
  17. 09 3月, 2013 16 次提交