- 04 6月, 2013 27 次提交
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由 Peter Maydell 提交于
If the user specifies a target list themselves, check each entry to make sure it's a target we recognise. This allows us to print a helpful error message, rather than falling through (where we would probably eventually end up hitting the uninformative "ERROR: Unsupported target CPU"). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1369062976-301-3-git-send-email-peter.maydell@linaro.org Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Peter Maydell 提交于
Autogenerate the default target list based on what files exist in default-configs; this allows us to remove one of the places that has to be kept up to date with a complete list of every target we support. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1369062976-301-2-git-send-email-peter.maydell@linaro.org Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Anthony Liguori 提交于
# By Peter Crosthwaite (20) and others # Via Peter Maydell * pmaydell/arm-devs.next: (24 commits) i.MX: Improve EPIT timer code. exynos4210.c: register rom_mem for memory migration hw/arm/exynos4210.c: convert chipid_and_omr to an mmio region i.MX: split GPT and EPIT timer implementation sd/sd.c: Fix "inquiry" ACMD41 sd/sdhci:ADMA: fix interrupt sd/sdhci.c: Fix bdata_read DPRINT message sd/sdhci: Fix Buffer Write Ready interrupt sd/sdhci.c: Only reset data_count on new commands xilinx_spips: lqspi: Fix byte/misaligned access xilinx_spips: lqspi: Push more data to tx-fifo xilinx_spips: Multiple debug verbosity levels xilinx_spips: Debug msgs for Snoop state xilinx_spips: Fix striping behaviour xilinx_spips: Fix CTRL register RW bits xilinx_spips: lqspi: Dont touch config register xilinx_spips: Implement automatic CS xilinx_spips: Add automatic start support xilinx_spips: Trash LQ page cache on mode change xilinx_spips: Fix QSPI FIFO size ... Message-id: 1370277021-26129-1-git-send-email-peter.maydell@linaro.org Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Jean-Christophe DUBOIS 提交于
* Unify function and type naming * use dynamic cast whenever possible * simplify Debug printf. * use new style device intialization. Signed-off-by: NJean-Christophe DUBOIS <jcd@tribudubois.net> Reviewed-by: NPeter Chubb <peter.chubb@nicta.com.au> Message-id: 1369839656-24466-1-git-send-email-jcd@tribudubois.net Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Igor Mitsyanko 提交于
Even if we do not register newly created RAM MemoryRegion for migration with vmstate_register_ram_global() function, ram_save_setup() still saves this region to snapshot file with empty idstr=="". Consequently this results in error during VM loading in ram_load(). Register rom_mem for migration. Signed-off-by: NIgor Mitsyanko <i.mitsyanko@samsung.com> Message-id: 1368199981-45292-3-git-send-email-i.mitsyanko@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Igor Mitsyanko 提交于
Exynos SoC was misusing memory_region_init_ram_ptr(): this interface can safely be used only for memory regions which size is a multiple of target page size. Change chipid_and_omr memory to an mmio region to fix this. Signed-off-by: NIgor Mitsyanko <i.mitsyanko@samsung.com> Message-id: 1368199981-45292-2-git-send-email-i.mitsyanko@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Jean-Christophe DUBOIS 提交于
There is no common code between these 2 timer implementation. So it is better to split them. Signed-off-by: NJean-Christophe DUBOIS <jcd@tribudubois.net> Message-id: 1368990197-19694-1-git-send-email-jcd@tribudubois.net Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
QEMU models two (of the three) ACMD41 has two modes, "inquiry" and "first". The selection logic for which of the two is incorrect - it compares != 0 for the entire argument value rather than only bits 23:0 as per the spec. Fix. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 3ef0a7fd1b2f3ebb23b4fdeabcc14caf3fad6d71.1369622254.git.peter.crosthwaite@xilinx.com Reviewed-by: NIgor Mitsyanko <i.mitsyanko@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
The end of transfer check was occurring and potentially returning before the interrupt flag was checked. This means the interrupt will be missed if it occurs on the last packet. Fix by checking for the interrupt before checking for the end of transfer. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NIgor Mitsyanko <i.mitsyanko@gmail.com> Message-id: 9969ec154777957ec738fc4e539d68e7494d0081.1369370934.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
This message was printing out the data in decimal only, which is not very friendly to the debugging developer. Add hex variant in parenthesis to make it consistent with other similar messages in this module. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NIgor Mitsyanko <i.mitsyanko@gmail.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: d624179649137832eaa8caa263ef9589b4395d5e.1369370934.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
This interrupt is not risen after the last block is written to sd. It is mutually exclusive with the end of transfer conditions. Fix. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NIgor Mitsyanko <i.mitsyanko@gmail.com> Message-id: 7ca9fd3e03ce1bec94aff08f607c15a0ec3d3371.1369370934.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
The data_count variable was being reset on every transfer, including DMA transfer resumptions. This is incorrect, it should only be set on a new command. Manifests as a bug when using ADMA and there is a timer delay between ADMA frames where the fifo is left in a non empty state. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NIgor Mitsyanko <i.mitsyanko@gmail.com> Message-id: 15a98609cc32315211b0963091a8efd67522e160.1369370934.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
The LQSPI bus attachment supports byte/halfword and misaligned accesses. Fixed. Refactored the LQSPI cache to be byte-wise instead of word wise accordingly. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 5ec47b13563ad2d22105a1f26186d7756718394b.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Do 16 words per fifo flush. Increases performance and decreases debug verbosity. This data depth has no real hardware analogue, so just go with something that has reasonable performance. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 5621ee4621941d3639b5cacfdec26bd3148f31d5.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
The debug printfs on every SPI operation is extremely verbose. Add a second level of debug for this. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: f63478b8e5b29cc011cdc10e29f8537bb2fc2b5e.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
This is worth keeping track of when debugging the device model. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: d3b44ecf23d671798b062eee5dc362c716ea54cd.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
The QSPI controller was using byte-wide stripes when striping across the two flashes in dual parallel mode. The real hardware however uses individual bit striping. QEMU misbehaves in the (corner) case where data is written/read in dual-parallel mode and read/written back in single mode. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 718a61df1bf746ec06f6da44d12f8317af7b08ce.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
The CTRL register was RAZ/WI on some of the RW bits. Even though the function behind these bits is invalid in QEMU, they should still be guest accessible. Fix. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: b7aaad93163ce4af0c428635804ac7b77a567b25.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
The LQSPI mode is supposed to work via the automatic CS mode feature rather than manipulate CS lines itself. Now that auto CS is implemented remove LQSPIs CS mode override logic. There is still a need to manipulate the U_PAGE bit in LQSPI config register to implement dual-stack mode however. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 000c8dd54df09523f17052638100722ef0f5a3af.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Implement the automatic CS control feature. If the MANUAL_CS bit is cleared then the chip select stay de-asserted as long as the tx FIFO is empty. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 1d67383adc42761af715a93f161344b9284dfc9a.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
SPI has a mode where it automatically starts based on tx fifo occupancy. Implemented. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: f4e9accb5de87b526fff6ed937f63278db76533b.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Invalidate the LQSPI cached page when transitioning into LQSPI mode. Otherwise there is a possibility that the controller will return stale data to the guest when transitioning back to LQ_MODE after a page program. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 677490a6ee1953fe5d366e599d665de645ac84db.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
QSPI has a bigger FIFO than the regular SPI controller. Differentiate between the two with correct FIFO sizes for each. This is the first piece of class data for SPIPS, so this patch sees the creation of the XilinxSPIPSClass definition and assoicated QOM constructs. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: acee25dd5e203215cbc15ca5d3cb5d5b2efebe7b.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
You really need this is you want to track a guest banging on LQSPI. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 26e508da4af11058d37daa777064c9e5c2a69abb.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
The real hardware does not produce interrupts in LQSPI mode. Inhibit generation of interrupts when the LQ_MODE bit is set. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: dff794a06872009ea7e5733ce6adcff94d18bbd0.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
By default these interrupts are clear on read. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 999ff0091ed3cc3969a431bf55c00ef934cecc8e.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Make SPI and QSPI different classes. QSPIPS is setup as a child of SPIPS. Only QSPI has the LQSPI functionality, so move all that to the child class. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 2cdd0cadb5ba77ca02fde5cae627852dc9a64c71.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 03 6月, 2013 11 次提交
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由 Ákos Kovács 提交于
Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: NÁkos Kovács <akoskovacs@gmx.com> Reviewed-by: NLaszlo Ersek <lersek@redhat.com> Message-id: 1367860492-3357-1-git-send-email-akoskovacs@gmx.com Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Anthony Liguori 提交于
# By Gerd Hoffmann (5) and others # Via Gerd Hoffmann * kraxel/usb.83: xhci: add live migration support xhci: add xhci_init_epctx xhci: add xhci_alloc_epctx xhci: add XHCISlot->addressed pci: add VMSTATE_MSIX host-libusb: Correct test for USB packet state Fix usage of USB_DEV_FLAG_IS_HOST flag. Message-id: 1370253951-12323-1-git-send-email-kraxel@redhat.com Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Anthony Liguori 提交于
# By Ed Maste (3) and others # Via Michael Tokarev * mjt/trivial-patches: do not check pointers after dereferencing them m25p80: Add Micron n25q032a qemu: fix out of tree cross compile slirp: cleanup leftovers from misc.h migration: Remove duplicate bandwidth_limit set docs: Fix typo and update file in migration configure: try pkg-config ncurses first rtc: remove rtc_set_date linux-user: Fix typo in comment configure: remove confusing file manipulation debugcon: fix compiler warning when open DEBUG_DEBUGCON debugcon: make debug message more readable debugcon: fix always print "addr=0x0, val=0x0" bug when use DEBUG_DEBUGCON Remove unnecessary break statements don't run pkg-config for features explicitly disabled Message-id: 51A9CCFB.1000109@msgid.tls.msk.ru Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Gerd Hoffmann 提交于
With all preparing pieces in place we can finally drop in the vmstate structs and the postload function. Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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由 Gerd Hoffmann 提交于
Factor out endpoint context initialization to a separate function. xhci live migration will need that too, in post_load. Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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由 Gerd Hoffmann 提交于
Factor out endpoint context allocation to a separate function. xhci live migration will need that too, in post_load. Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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由 Gerd Hoffmann 提交于
Preparing for live-migration support, post_load will need that. Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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由 Gerd Hoffmann 提交于
Using a trick cut+pasted from vmstate_scsi_device to wind up msix_save and msix_load. Signed-off-by: NGerd Hoffmann <kraxel@redhat.com> Acked-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Ed Maste 提交于
USB_RET_ASYNC is -6, so inflight was always false. Signed-off-by: NEd Maste <emaste@freebsd.org> Cc: qemu-stable@nongnu.org Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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由 Michael Marineau 提交于
USB_DEV_FLAG_IS_HOST is the bit number, not value. Booting with a "Fitbit Base Station" USB dongle was triggering this assert. Signed-off-by: NMichael Marineau <mike@marineau.org> Cc: qemu-stable@nongnu.org Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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由 Mark Cave-Ayland 提交于
Commit d08151bf (conversion of tcx to the memory API) broke the 24-bit mode of the tcx display adapter by accidentally passing in the final address of the dirty region to memory_region_reset_dirty() instead of its size. Signed-off-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 01 6月, 2013 2 次提交
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由 Paolo Bonzini 提交于
Two instances, both spotted by Coverity. In one, two blocks were swapped. In the other, the check is not needed anymore. Cc: qemu-stable@nongnu.org Cc: qemu-trivial@nongnu.org Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Reviewed-by: NEric Blake <eblake@redhat.com> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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由 Ed Maste 提交于
Based on the datasheet at http://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/Serial%20NOR/N25Q/n25q_32mb_1_8v_65nm.pdfSigned-off-by: NEd Maste <emaste@freebsd.org> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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