1. 28 10月, 2016 31 次提交
  2. 27 10月, 2016 3 次提交
    • P
      Merge remote-tracking branch 'remotes/rth/tags/pull-atomic-20161026' into staging · 5929d7e8
      Peter Maydell 提交于
      cmpxchg emulation of atomics, v8
      
      # gpg: Signature made Wed 26 Oct 2016 16:30:03 BST
      # gpg:                using RSA key 0xAD1270CC4DD0279B
      # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
      # gpg:                 aka "Richard Henderson <rth@redhat.com>"
      # gpg:                 aka "Richard Henderson <rth@twiddle.net>"
      # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC  16A4 AD12 70CC 4DD0 279B
      
      * remotes/rth/tags/pull-atomic-20161026: (37 commits)
        target-alpha: Emulate LL/SC using cmpxchg helpers
        target-alpha: Introduce MMU_PHYS_IDX
        target-arm: remove EXCP_STREX + cpu_exclusive_{test, info}
        linux-user: remove handling of aarch64's EXCP_STREX
        linux-user: remove handling of ARM's EXCP_STREX
        target-arm: emulate aarch64's LL/SC using cmpxchg helpers
        target-arm: emulate SWP with atomic_xchg helper
        target-arm: emulate LL/SC using cmpxchg helpers
        target-arm: Rearrange aa32 load and store functions
        tests: add atomic_add-bench
        target-i386: remove helper_lock()
        target-i386: emulate XCHG using atomic helper
        target-i386: emulate LOCK'ed BTX ops using atomic helpers
        target-i386: emulate LOCK'ed XADD using atomic helper
        target-i386: emulate LOCK'ed NEG using cmpxchg helper
        target-i386: emulate LOCK'ed NOT using atomic helper
        target-i386: emulate LOCK'ed INC using atomic helper
        target-i386: emulate LOCK'ed OP instructions using atomic helpers
        target-i386: emulate LOCK'ed cmpxchg using cmpxchg helpers
        tcg: Emit barriers with parallel_cpus
        ...
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      5929d7e8
    • P
      Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging · 8f9d84df
      Peter Maydell 提交于
      # gpg: Signature made Wed 26 Oct 2016 03:19:06 BST
      # gpg:                using RSA key 0xEF04965B398D6211
      # gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>"
      # gpg: WARNING: This key is not certified with sufficiently trusted signatures!
      # gpg:          It is not certain that the signature belongs to the owner.
      # Primary key fingerprint: 215D 46F4 8246 689E C77F  3562 EF04 965B 398D 6211
      
      * remotes/jasowang/tags/net-pull-request:
        colo-proxy: fix memory leak
        net: rtl8139: limit processing of ring descriptors
        net: vmxnet: initialise local tx descriptor
        e1000e: Don't zero out buffer address in rx descriptor
        net: rocker: set limit to DMA buffer size
        net: eepro100: fix memory leak in device uninit
        tap-bsd: OpenBSD uses tap(4) now
        net: pcnet: fix source formatting and indentation
        net: pcnet: check rx/tx descriptor ring length
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      8f9d84df
    • P
      Merge remote-tracking branch 'remotes/vivier/tags/m68k-part1-pull-request' into staging · 991a97ac
      Peter Maydell 提交于
      # gpg: Signature made Tue 25 Oct 2016 19:58:46 BST
      # gpg:                using RSA key 0xF30C38BD3F2FBE3C
      # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>"
      # gpg:                 aka "Laurent Vivier <laurent@vivier.eu>"
      # gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>"
      # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C
      
      * remotes/vivier/tags/m68k-part1-pull-request: (23 commits)
        target-m68k: Optimize gen_flush_flags
        target-m68k: Optimize some comparisons
        target-m68k: Use setcond for scc
        target-m68k: Introduce DisasCompare
        target-m68k: Reorg flags handling
        target-m68k: Remove incorrect clearing of cc_x
        target-m68k: Some fixes to SR and flags management
        target-m68k: Print flags properly
        target-m68k: update CPU flags management
        target-m68k: don't update cc_dest in helpers
        target-m68k: update move to/from ccr/sr
        target-m68k: remove m68k_cpu_exec_enter() and m68k_cpu_exec_exit()
        target-m68k: Replace helper_xflag_lt with setcond
        target-m68k: allow to update flags with operation on words and bytes
        target-m68k: REG() macro cleanup
        target-m68k: set PAGE_BITS to 12 for m68k
        target-m68k: define operand sizes
        target-m68k: set disassembler mode to 680x0 or coldfire
        target-m68k: introduce read_imXX() functions
        target-m68k: manage scaled index
        ...
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      991a97ac
  3. 26 10月, 2016 6 次提交
    • R
      target-alpha: Emulate LL/SC using cmpxchg helpers · ed283916
      Richard Henderson 提交于
      Emulating LL/SC with cmpxchg is not correct, since it can
      suffer from the ABA problem.  However, portable parallel
      code is written assuming only cmpxchg which means that in
      practice this is a viable alternative.
      Signed-off-by: NRichard Henderson <rth@twiddle.net>
      ed283916
    • R
      target-alpha: Introduce MMU_PHYS_IDX · 6a73ecf5
      Richard Henderson 提交于
      Rather than using helpers for physical accesses, use a mmu index.
      The primary cleanup is with store-conditional on physical addresses.
      Signed-off-by: NRichard Henderson <rth@twiddle.net>
      6a73ecf5
    • E
      target-arm: remove EXCP_STREX + cpu_exclusive_{test, info} · 05188cc7
      Emilio G. Cota 提交于
      The exception is not emitted anymore; remove it and the associated
      TCG variables.
      Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
      Signed-off-by: NEmilio G. Cota <cota@braap.org>
      Signed-off-by: NRichard Henderson <rth@twiddle.net>
      Message-Id: <1467054136-10430-31-git-send-email-cota@braap.org>
      05188cc7
    • E
      linux-user: remove handling of aarch64's EXCP_STREX · f4e6eb7f
      Emilio G. Cota 提交于
      The exception is not emitted anymore.
      Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
      Signed-off-by: NEmilio G. Cota <cota@braap.org>
      Signed-off-by: NRichard Henderson <rth@twiddle.net>
      Message-Id: <1467054136-10430-30-git-send-email-cota@braap.org>
      f4e6eb7f
    • E
      linux-user: remove handling of ARM's EXCP_STREX · b50b82fc
      Emilio G. Cota 提交于
      The exception is not emitted anymore.
      Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
      Signed-off-by: NEmilio G. Cota <cota@braap.org>
      Signed-off-by: NRichard Henderson <rth@twidle.net>
      Message-Id: <1467054136-10430-29-git-send-email-cota@braap.org>
      b50b82fc
    • E
      target-arm: emulate aarch64's LL/SC using cmpxchg helpers · 1dd089d0
      Emilio G. Cota 提交于
      Emulating LL/SC with cmpxchg is not correct, since it can
      suffer from the ABA problem. Portable parallel code, however,
      is written assuming only cmpxchg--and not LL/SC--is available.
      This means that in practice emulating LL/SC with cmpxchg is
      a viable alternative.
      
      The appended emulates LL/SC pairs in aarch64 with cmpxchg helpers.
      This works in both user and system mode. In usermode, it avoids
      pausing all other CPUs to perform the LL/SC pair. The subsequent
      performance and scalability improvement is significant, as the
      plots below show. They plot the throughput of atomic_add-bench
      compiled for ARM and executed on a 64-core x86 machine.
      
      Hi-res plots: http://imgur.com/a/JVc8Y
      
                      atomic_add-bench: 1000000 ops/thread, [0,1] range
      
        18 ++---------+----------+---------+----------+----------+----------+---++
           +cmpxchg +-E--+       +         +          +          +          +    |
        16 ++master +-H--+                                                      ++
           ||                                                                    |
        14 ++                                                                   ++
           | |                                                                   |
        12 ++|                                                                  ++
           | |                                                                   |
        10 ++++                                                                 ++
         8 ++E                                                                  ++
           |+++                                                                  |
         6 ++ |                                                                 ++
           |  |                                                                  |
         4 ++ |                                                                 ++
           |   |                                                                 |
         2 +H++E+---                                                            ++
           + |     +E++----+E+---+--+E+----++E+------+E+------+E++----+E+---+--+E|
         0 ++H-H----H-+-----H----+---------+----------+----------+----------+---++
           0          10         20        30         40         50         60
                                      Number of threads
      
                      atomic_add-bench: 1000000 ops/thread, [0,2] range
      
        18 ++---------+----------+---------+----------+----------+----------+---++
           +cmpxchg +-E--+       +         +          +          +          +    |
        16 ++master +-H--+                                                      ++
           | |                                                                   |
        14 ++E                                                                  ++
           | |                                                                   |
        12 ++|                                                                  ++
           |+++                                                                  |
        10 ++ |                                                                 ++
         8 ++ |                                                                 ++
           |  |                                                                  |
         6 ++ |                                                                 ++
           |   |                                                                 |
         4 ++  |                                                                ++
           |  +E+---                                                             |
         2 +H+     +E+-----+++              +++      +++   ---+E+-----+E+------+++
           +++        +    +E+---+--+E+----++E+------+E+---   ++++    +++   +  +E|
         0 ++H-H----H-+-----H----+---------+----------+----------+----------+---++
           0          10         20        30         40         50         60
                                      Number of threads
      
                     atomic_add-bench: 1000000 ops/thread, [0,128] range
      
        70 ++---------+----------+---------+----------+----------+----------+---++
           +cmpxchg +-E--+       +         +          +          +          +    |
        60 ++master +-H--+                  +++            ---+E+-----+E+------+E+
           |                        +E+------E-------+E+---                      |
           |                     ---        +++                                  |
        50 ++              +++---                                               ++
           |              -+E+                                                   |
        40 ++      +++----                                                      ++
           |        E-                                                           |
           |      --|                                                            |
        30 ++   -- +++                                                          ++
           |  +E+                                                                |
        20 ++E+                                                                 ++
           |E+                                                                   |
           |                                                                     |
        10 ++                                                                   ++
           +          +          +         +          +          +          +    |
         0 +HH-H----H-+-----H----+---------+----------+----------+----------+---++
           0          10         20        30         40         50         60
                                      Number of threads
      
                    atomic_add-bench: 1000000 ops/thread, [0,1024] range
      
        160 ++---------+---------+----------+---------+----------+----------+---++
            +cmpxchg +-E--+      +          +         +          +          +    |
        140 ++master +-H--+                                           +++      +++
            |                                                -+E+-----+E+-------E|
        120 ++                                       +++ ----                  +++
            |                                +++  ----E--                        |
        100 ++                              --E---   +++                        ++
            |                       +++ ---- +++                                 |
         80 ++                     --E--                                        ++
            |                  ---- +++                                          |
            |              -+E+                                                  |
         60 ++         ---- +++                                                 ++
            |      +E+-                                                          |
         40 ++   --                                                             ++
            |  +E+                                                               |
         20 +EE+                                                                ++
            +++        +         +          +         +          +          +    |
          0 +HH-H---H--+-----H---+----------+---------+----------+----------+---++
            0          10        20         30        40         50         60
                                      Number of threads
      
      [rth: Rearrange 128-bit cmpxchg helper.  Enforce alignment on LL.]
      Signed-off-by: NEmilio G. Cota <cota@braap.org>
      Message-Id: <1467054136-10430-28-git-send-email-cota@braap.org>
      Signed-off-by: NRichard Henderson <rth@twiddle.net>
      1dd089d0