- 29 5月, 2015 8 次提交
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由 Shannon Zhao 提交于
RSDT points to other tables FADT, MADT, GTDT. This code is shared with x86. Here we still use RSDT as UEFI puts ACPI tables below 4G address space, and UEFI ignore the RSDT or XSDT. Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-12-git-send-email-zhaoshenglong@huawei.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Shannon Zhao 提交于
ACPI v5.1 defines GTDT for ARM devices as a place to describe timer related information in the system. The Arch Timer interrupts must be provided for GTDT. Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-11-git-send-email-zhaoshenglong@huawei.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Shannon Zhao 提交于
MADT describes GIC enabled ARM platforms. The GICC and GICD subtables are used to define the GIC regions. Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-10-git-send-email-zhaoshenglong@huawei.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Shannon Zhao 提交于
In the case of mach virt, it is used to set the Hardware Reduced bit and enable PSCI SMP booting through HVC. So ignore FACS and FADT points to DSDT. Update the header definitions for FADT taking into account the new additions of ACPI v5.1 in `include/hw/acpi/acpi-defs.h` Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Message-id: 1432522520-8068-9-git-send-email-zhaoshenglong@huawei.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Shannon Zhao 提交于
DSDT consists of the usual common table header plus a definition block in AML encoding which describes all devices in the platform. After initializing DSDT with header information the namespace is created which is followed by the device encodings. The devices are described using the Resource Template for the 32-Bit Fixed Memory Range and the Extended Interrupt Descriptors. Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-8-git-send-email-zhaoshenglong@huawei.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Shannon Zhao 提交于
Introduce a preliminary framework in virt-acpi-build.c with the main ACPI build functions. It exposes the generated ACPI contents to guest over fw_cfg. The required ACPI v5.1 tables for ARM are: - RSDP: Initial table that points to XSDT - RSDT: Points to FADT GTDT MADT tables - FADT: Generic information about the machine - GTDT: Generic timer description table - MADT: Multiple APIC description table - DSDT: Holds all information about system devices/peripherals, pointed by FADT Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Reviewed-by: NIgor Mammedov <imammedo@redhat.com> Message-id: 1432522520-8068-5-git-send-email-zhaoshenglong@huawei.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Shannon Zhao 提交于
To generate ACPI table for PCIe controller, we need the base and size of the PCIe ranges. Record these ranges in MemMapEntry array, then we could share and use them for generating ACPI table. Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Message-id: 1432522520-8068-4-git-send-email-zhaoshenglong@huawei.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Shannon Zhao 提交于
Move some common definitions to virt.h. These will be used by generating ACPI tables. Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-3-git-send-email-zhaoshenglong@huawei.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 18 5月, 2015 8 次提交
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由 Peter Crosthwaite 提交于
Add bootloader support using standard ARM bootloader. Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Tested-by: NAlistair Francis <alistair.francis@xilinx.com> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: b829abaf2b70d02b28e79301553cbd74afc416a1.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Zynq MPSoC supports external DDR RAM. Add a RAM at 0 to the model. Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Tested-by: NAlistair Francis <alistair.francis@xilinx.com> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 2c25e2a4198402a6477aef2975d5df7c415dd341.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Add a machine model for the Xilinx ZynqMP SoC EP108 board. Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: NAlistair Francis <alistair.francis@xilinx.com> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 3896b34c862f370dc0679e4428bf3848d1f9f83c.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
There are 2x Cadence UARTs in Zynq MP. Add them. Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Tested-by: NAlistair Francis <alistair.francis@xilinx.com> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: e30795536f77599fabc1052278d846ccd52322e2.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
There are 4x Cadence GEMs in ZynqMP. Add them. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Tested-by: NAlistair Francis <alistair.francis@xilinx.com> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 7d3e68e5495d145255f0ee567046415e3a26d67e.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Connect the GPIO outputs from the individual CPUs for the timers to the GIC. Tested-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: a7866a4f0c903c91fa3034210b4d2879aa4bfcb9.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Add the GIC and connect IRQ outputs to the CPUs. The GIC regions are under-decoded through a 64k address region so implement aliases accordingly. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 5853189965728d676106d9e94e76b9bb87981cb5.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
With quad Cortex-A53 CPUs. Use SMC PSCI, with the standard policy of secondaries starting in power-off. Tested-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: a16202a6c7b79e446e5289d38cb18d2ee4b897a0.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 12 5月, 2015 3 次提交
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由 Peter Maydell 提交于
Connect FIQ output of the GIC CPU interfaces to the CPUs. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-18-git-send-email-peter.maydell@linaro.org
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由 Fabian Aggeler 提交于
Connect FIQ output of the GIC CPU interfaces to the CPUs. Signed-off-by: NFabian Aggeler <aggelerf@ethz.ch> Signed-off-by: NGreg Bellows <greg.bellows@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-17-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-3-git-send-email-greg.bellows@linaro.org [PMM: minor format tweak] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Greg Bellows 提交于
Connect FIQ output of the GIC CPU interfaces to the CPUs. Signed-off-by: NGreg Bellows <greg.bellows@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-16-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-4-git-send-email-greg.bellows@linaro.org [PMM: minor format tweak] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 28 4月, 2015 3 次提交
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由 Stefan Hajnoczi 提交于
There are a number of ffs(3) callers that do roughly: bit = ffs(val); if (bit) { do_something(bit - 1); } This pattern can be converted to ctz32() like this: zeroes = ctz32(val); if (zeroes != 32) { do_something(zeroes); } Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com> Message-id: 1427124571-28598-6-git-send-email-stefanha@redhat.com Signed-off-by: NKevin Wolf <kwolf@redhat.com>
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由 Stefan Hajnoczi 提交于
This commit was generated mechanically by coccinelle from the following semantic patch: @@ expression val; @@ - (ffs(val) - 1) + ctz32(val) The call sites have been audited to ensure the ffs(0) - 1 == -1 case never occurs (due to input validation, asserts, etc). Therefore we don't need to worry about the fact that ctz32(0) == 32. Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com> Message-id: 1427124571-28598-5-git-send-email-stefanha@redhat.com Signed-off-by: NKevin Wolf <kwolf@redhat.com>
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由 Stefan Hajnoczi 提交于
It is not clear from the code how a 0 parameter should be handled by the hardware. Keep the same behavior as ffs(0) - 1 == -1. Cc: Andrzej Zaborowski <balrog@zabor.org> Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com> Message-id: 1427124571-28598-3-git-send-email-stefanha@redhat.com Signed-off-by: NKevin Wolf <kwolf@redhat.com>
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- 26 4月, 2015 2 次提交
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由 Sergey Fedorov 提交于
Rename the field holding CPACR_EL1 system register state in AArch64 naming style. Signed-off-by: NSergey Fedorov <serge.fdrv@gmail.com> [PMM: also fixed a couple of missed occurrences in cpu.c] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Switch all the uses of ld/st*_phys to address_space_ld/st*, except for those cases where the address space is the CPU's (ie cs->as). This was done with the following script which generates a Coccinelle patch. A few over-80-columns lines in the result were rewrapped by hand where Coccinelle failed to do the wrapping automatically, as well as one location where it didn't put a line-continuation '\' when wrapping lines on a change made to a match inside a macro definition. ===begin=== #!/bin/sh -e # Usage: # ./ldst-phys.spatch.sh > ldst-phys.spatch # spatch -sp_file ldst-phys.spatch -dir . | sed -e '/^+/s/\t/ /g' > out.patch # patch -p1 < out.patch for FN in ub uw_le uw_be l_le l_be q_le q_be uw l q; do cat <<EOF @ cpu_matches_ld_${FN} @ expression E1,E2; identifier as; @@ ld${FN}_phys(E1->as,E2) @ other_matches_ld_${FN} depends on !cpu_matches_ld_${FN} @ expression E1,E2; @@ -ld${FN}_phys(E1,E2) +address_space_ld${FN}(E1,E2, MEMTXATTRS_UNSPECIFIED, NULL) EOF done for FN in b w_le w_be l_le l_be q_le q_be w l q; do cat <<EOF @ cpu_matches_st_${FN} @ expression E1,E2,E3; identifier as; @@ st${FN}_phys(E1->as,E2,E3) @ other_matches_st_${FN} depends on !cpu_matches_st_${FN} @ expression E1,E2,E3; @@ -st${FN}_phys(E1,E2,E3) +address_space_st${FN}(E1,E2,E3, MEMTXATTRS_UNSPECIFIED, NULL) EOF done ===endit=== Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
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- 09 4月, 2015 1 次提交
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由 Dirk Müller 提交于
Commit 0b183fc8:"memory: move mem_path handling to memory_region_allocate_system_memory" split memory_region_init_ram and memory_region_init_ram_from_file. Also it moved mem-path handling a step up from memory_region_init_ram to memory_region_allocate_system_memory. Therefore for any board that uses memory_region_init_ram directly, -mem-path is not supported. Fix this by replacing memory_region_init_ram with memory_region_allocate_system_memory. Signed-off-by: NDirk Mueller <dmueller@suse.com> Message-id: CAL5wTH4UHYKpJF=dLJfFzxpufjY189chnCow47-ySuLf8GLbug@mail.gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 02 4月, 2015 9 次提交
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由 Markus Armbruster 提交于
Device models aren't supposed to go on fishing expeditions for backends. They should expose suitable properties for the user to set. For onboard devices, board code sets them. A number of sysbus devices pick up block backends in their init() / instance_init() methods with drive_get_next() instead: sl-nand, milkymist-memcard, pl181, generic-sdhci. Likewise, a number of sysbus devices pick up character backends in their init() / realize() methods with qemu_char_get_next_serial(): cadence_uart, digic-uart, etraxfs,serial, lm32-juart, lm32-uart, milkymist-uart, pl011, stm32f2xx-usart, xlnx.xps-uartlite. All these mistakes are already marked FIXME. See the commit that added these FIXMEs for a more detailed explanation of what's wrong. Fortunately, only machines ppce500 and pseries-* support -device with sysbus devices, and none of the devices above is supported with these machines. Set cannot_instantiate_with_device_add_yet to preserve our luck. Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Cc: Antony Pavlov <antonynpavlov@gmail.com> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Michael Walle <michael@walle.cc> Signed-off-by: NMarkus Armbruster <armbru@redhat.com>
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由 Markus Armbruster 提交于
NICs defined with -net nic are for board initialization to wire up. Board code examines nd_table[] to find them, and creates devices with their qdev NIC properties set accordingly. Except "allwinner-a10" goes on a fishing expedition for NIC configuration instead of exposing the usual NIC properties for board code to set: it uses nd_table[0] in its instance_init() method. Picking up the first -net nic option's configuration that way works when the device is created by board code. But it's inappropriate for -device and device_add. Not only is it inconsistent with how the other block device models work (they get their configuration from properties "mac", "vlan", "netdev"), it breaks when nd_table[0] has been picked up by the board or a previous -device / device_add already. Example: $ qemu-system-arm -S -M cubieboard -device allwinner-a10 qemu-system-arm: -device allwinner-a10: Property 'allwinner-emac.netdev' can't take value 'hub0port0', it's in use Aborted (core dumped) It also breaks in other entertaining ways: $ qemu-system-arm -M highbank -device allwinner-a10 qemu-system-arm: -device allwinner-a10: Unsupported NIC model: xgmac $ qemu-system-arm -M highbank -net nic,model=allwinner-emac -device allwinner-a10 qemu-system-arm: Unsupported NIC model: allwinner-emac Mark the mistake with a FIXME comment. Cc: Li Guang <lig.fnst@cn.fujitsu.com> Signed-off-by: NMarkus Armbruster <armbru@redhat.com>
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由 Markus Armbruster 提交于
Character devices defined with -serial and -parallel are for board initialization to wire up. Board code examines serial_hds[] and parallel_hds[] to find them, and creates devices with their qdev chardev properties set accordingly. Except a few devices go on a fishing expedition for a suitable backend instead of exposing a chardev property for board code to set: they use serial_hds[] (often via qemu_char_get_next_serial()) or parallel_hds[] in their realize() or init() method to connect to a backend. Picking up backends that way works when the devices are created by board code. But it's inappropriate for -device or device_add. Not only is it inconsistent with how the other characrer device models work (they connect to a backend explicitly identified by a "chardev" property), it breaks when the backend has been picked up by the board or a previous -device / device_add already. Example: $ qemu-system-ppc64 -M bamboo -S -device i82378 -device pc87312 -device pc87312 qemu-system-ppc64: -device pc87312: Property 'isa-parallel.chardev' can't take value 'parallel0', it's in use Mark them with suitable FIXME comments. Cc: Li Guang <lig.fnst@cn.fujitsu.com> Cc: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Cc: Antony Pavlov <antonynpavlov@gmail.com> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Michael Walle <michael@walle.cc> Cc: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Cc: "Andreas Färber" <andreas.faerber@web.de> Signed-off-by: NMarkus Armbruster <armbru@redhat.com>
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由 Markus Armbruster 提交于
Drives defined with if!=none are for board initialization to wire up. Board code calls drive_get() or similar to find them, and creates devices with their qdev drive properties set accordingly. Except a few devices go on a fishing expedition for a suitable backend instead of exposing a drive property for board code to set: they call driver_get() or drive_get_next() in their realize() or init() method to implicitly connect to the "next" backend with a certain interface type. Picking up backends that way works when the devices are created by board code. But it's inappropriate for -device or device_add. Not only is this inconsistent with how the other block device models work (they connect to a backend explicitly identified by a "drive" property), it breaks when the "next" backend has been picked up by the board already. Example: $ qemu-system-arm -S -M connex -pflash flash.img -device ssi-sd Aborted (core dumped) Mark them with suitable FIXME comments. Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Cc: "Andreas Färber" <andreas.faerber@web.de> Cc: Michael Walle <michael@walle.cc> Signed-off-by: NMarkus Armbruster <armbru@redhat.com>
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由 Peter Maydell 提交于
Commits 6e05a12f and db25a158 both attempt to fix the same "failed to free memory containing flash filename" bug, with the effect that when they were both applied we ended up freeing the memory twice. Delete the spurious extra free. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NStefan Weil <sw@weilnetz.de> Message-id: 1427968334-14527-1-git-send-email-peter.maydell@linaro.org
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由 Shannon Zhao 提交于
As 4de9a883(hw/arm/virt: Fix memory leak reported by Coverity) and 6e05a12f(arm: fix memory leak) both handle the memory leak reported by Coverity, this cause qemu corruption due to double free. Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Reviewed-by: NStefan Weil <sw@weilnetz.de> Message-id: 1427944026-8968-1-git-send-email-zhaoshenglong@huawei.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Stefan Weil 提交于
As the conditional statement had to be split anyway, we can also add a better error report message. Signed-off-by: NStefan Weil <sw@weilnetz.de> Message-id: 1426877982-3603-1-git-send-email-sw@weilnetz.de Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Stefan Weil 提交于
As the conditional statement had to be split anyway, we can also add a better error report message. Signed-off-by: NStefan Weil <sw@weilnetz.de> Message-id: 1426877963-3556-1-git-send-email-sw@weilnetz.de Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Stefan Weil 提交于
Coverity reports a resource leak for sysboot_filename which is allocated by qemu_find_file. In addition, that name is used to get the size of the image, but a different image name was used to load it. In addition, instead of passing the maximum allowed image size the actual image size was passed to load_image_targphys. Fix all three issues. Signed-off-by: NStefan Weil <sw@weilnetz.de> Message-id: 1426326781-2488-1-git-send-email-sw@weilnetz.de Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 19 3月, 2015 4 次提交
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由 zhanghailiang 提交于
This is a continuation of the work started in commit 565f65d2: "error: Use error_report_err() where appropriate" Signed-off-by: Nzhanghailiang <zhang.zhanghailiang@huawei.com> Reviewed-by: NEric Blake <eblake@redhat.com> Reviewed-by: NMarkus Armbruster <armbru@redhat.com> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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由 Gonglei 提交于
Cc: Michael Tokarev <mjt@tls.msk.ru> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: NGonglei <arei.gonglei@huawei.com> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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由 Stefan Weil 提交于
Sparse report: arm/nseries.c:1406:5: warning: returning void-valued expression arm/nseries.c:1411:5: warning: returning void-valued expression Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: NStefan Weil <sw@weilnetz.de> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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由 Stefan Weil 提交于
Sparse report: arm/omap1.c:1015:9: warning: returning void-valued expression arm/omap1.c:1084:9: warning: returning void-valued expression arm/omap1.c:1178:9: warning: returning void-valued expression arm/omap1.c:1287:9: warning: returning void-valued expression arm/omap1.c:1382:9: warning: returning void-valued expression arm/omap1.c:1650:9: warning: returning void-valued expression arm/omap1.c:1778:9: warning: returning void-valued expression arm/omap1.c:1985:9: warning: returning void-valued expression arm/omap1.c:210:9: warning: returning void-valued expression arm/omap1.c:2213:9: warning: returning void-valued expression arm/omap1.c:2352:9: warning: returning void-valued expression arm/omap1.c:2447:9: warning: returning void-valued expression arm/omap1.c:2640:9: warning: returning void-valued expression arm/omap1.c:317:9: warning: returning void-valued expression arm/omap1.c:3413:13: warning: returning void-valued expression arm/omap1.c:3414:13: warning: returning void-valued expression arm/omap1.c:3415:14: warning: returning void-valued expression arm/omap1.c:3589:9: warning: returning void-valued expression arm/omap1.c:443:9: warning: returning void-valued expression arm/omap1.c:588:9: warning: returning void-valued expression arm/omap1.c:860:9: warning: returning void-valued expression arm/omap2.c:1362:9: warning: returning void-valued expression arm/omap2.c:450:9: warning: returning void-valued expression arm/omap2.c:695:9: warning: returning void-valued expression arm/omap2.c:760:9: warning: returning void-valued expression hw/char/omap_uart.c:115:9: warning: returning void-valued expression hw/display/omap_dss.c:1019:9: warning: returning void-valued expression hw/display/omap_dss.c:215:9: warning: returning void-valued expression hw/display/omap_dss.c:380:9: warning: returning void-valued expression hw/display/omap_dss.c:739:9: warning: returning void-valued expression hw/display/omap_dss.c:931:9: warning: returning void-valued expression hw/dma/omap_dma.c:139:5: warning: returning void-valued expression hw/dma/omap_dma.c:1505:9: warning: returning void-valued expression hw/dma/omap_dma.c:1860:9: warning: returning void-valued expression hw/gpio/omap_gpio.c:116:9: warning: returning void-valued expression hw/misc/omap_gpmc.c:627:9: warning: returning void-valued expression hw/misc/omap_l4.c:85:9: warning: returning void-valued expression hw/misc/omap_sdrc.c:95:9: warning: returning void-valued expression hw/misc/omap_tap.c:98:9: warning: returning void-valued expression hw/sd/omap_mmc.c:409:9: warning: returning void-valued expression hw/ssi/omap_spi.c:229:9: warning: returning void-valued expression hw/timer/omap_gptimer.c:447:9: warning: returning void-valued expression Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: NStefan Weil <sw@weilnetz.de> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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- 11 3月, 2015 2 次提交
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由 Jan Kiszka 提交于
This allows to use the SD card emulation of the board: Forward the signals from the pl181 top the CP control register emulation, report the current state via CP_INTREG, deliver CARDIN IRQ to the secondary interrupt controller and also support clearing that line via CP_INTREG. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Message-id: c55d9fb28d19ec83625cb0074b3b6f2e5958caf6.1426004843.git.jan.kiszka@siemens.com Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Jan Kiszka 提交于
No new features yet, just encapsulation. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Message-id: 3829c7c7e01cd3ccf15a1198f114e4d675974ae0.1426004843.git.jan.kiszka@siemens.com Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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